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https://github.com/stnolting/neorv32.git
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minor edits
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stnolting
parent
b032855eca
commit
ed40bdf0b7
3 changed files with 67 additions and 67 deletions
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@ -63,9 +63,6 @@ architecture neorv32_devnull_rtl of neorv32_devnull is
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-- configuration --
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constant sim_output_en_c : boolean := true; -- output lowest byte as char to simulator
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-- text.io --
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file file_devnull_out : text open write_mode is "neorv32.devnull.out";
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(devnull_size_c); -- low address boundary bit
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@ -83,6 +80,7 @@ begin
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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file file_devnull_out : text open write_mode is "neorv32.devnull.out";
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variable i : integer;
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variable la, lb : line; -- we need to variables here since "writeline" seems to flush the source variable
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begin
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@ -95,7 +93,7 @@ begin
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if (i >= 128) then -- out of range?
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i := 0;
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end if;
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if (i /= 10) and (i /= 13) then -- skip linebreaks
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if (i /= 10) and (i /= 13) then -- skip line breaks - they are issued via "writeline"
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write(la, character'val(i));
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write(lb, character'val(i));
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end if;
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@ -172,7 +172,7 @@ package neorv32_package is
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constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_rd_c : natural := 33; -- read data request
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constant ctrl_bus_wr_c : natural := 34; -- write data request
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (output PC, otherwise output MAR)
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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@ -405,6 +405,64 @@ package neorv32_package is
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);
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end component;
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu
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generic (
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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-- external interrupts --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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end component;
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-- Component: CPU Control -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_control
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@ -602,64 +660,6 @@ package neorv32_package is
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);
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end component;
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-- Component: CPU Top Entity --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu
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generic (
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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-- external interrupts --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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end component;
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-- Component: Processor-internal instruction memory (IMEM) --------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_imem
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@ -949,8 +949,8 @@ package neorv32_package is
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);
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end component;
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-- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
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-- -------------------------------------------------------------------------------------------
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---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
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---- -------------------------------------------------------------------------------------------
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component neorv32_devnull
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port (
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-- host access --
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@ -587,7 +587,9 @@ begin
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clic_xirq(6) <= ext_irq_i(0);
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clic_xirq(7) <= ext_irq_i(1); -- lowest priority
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ext_ack_o <= clic_xirq(7 downto 6); -- external interrupt request acknowledge
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-- external interrupt request acknowledge --
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ext_ack_o(0) <= clic_xack(6);
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ext_ack_o(1) <= clic_xack(7);
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neorv32_clic_inst_false:
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if (IO_CLIC_USE = false) generate
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@ -848,7 +850,7 @@ begin
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ack_o => devnull_ack -- transfer acknowledge
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);
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end generate;
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neorv32_devnull_inst_false:
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if (IO_DEVNULL_USE = false) generate
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devnull_rdata <= (others => '0');
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