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🚀 preparing release v1.9.8
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4 changed files with 4 additions and 3 deletions
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Link |
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|:----:|:-------:|:--------|:----:|
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| 04.04.2024 | [**:rocket:1.9.8**](https://github.com/stnolting/neorv32/releases/tag/v1.9.8) | **New release** | |
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| 04.04.2024 | 1.9.7.10 | extend SPI and SDI interrupt conditions | [#870](https://github.com/stnolting/neorv32/pull/870) |
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| 04.04.2024 | 1.9.7.9 | RISC-V `B` ISA extension (bit-manipulation) only contains sub-extensions `Zba+Zbb+Zbs`; :warning: remove support for `Zbc` ISA extension | [#869](https://github.com/stnolting/neorv32/pull/869) |
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| 03.04.2024 | 1.9.7.8 | split SLINK interrupt into two individual FIRQs (SLINK RX and SLINK TX) | [#868](https://github.com/stnolting/neorv32/pull/868) |
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@ -1,6 +1,6 @@
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:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety
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:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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:revnumber: v1.9.7
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:revnumber: v1.9.8
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:doctype: book
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:sectnums:
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:stem:
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@ -52,7 +52,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090710"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090800"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -4,7 +4,7 @@
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<vendor>stnolting</vendor>
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<name>neorv32</name>
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<series>RISC-V</series>
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<version>1.9.7</version>
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<version>1.9.8</version>
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<description>The NEORV32 RISC-V Processor</description>
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<!-- CPU core -->
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