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[docs] register maps cleanup

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stnolting 2023-03-04 11:35:48 +01:00
parent 747fcd5577
commit f5047efce6
16 changed files with 205 additions and 205 deletions
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6
docs/datasheet/soc_buskeeper.adoc
View file

@ -49,11 +49,11 @@ the CPU's PMP logic).
**Register Map**
.BUSKEEPER register map (`struct NEORV32_BUSKEEPER`)
[cols="<2,<2,<4,^1,<4"]
[cols="<3,<2,<4,^1,<4"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.2+<| `0xffffff78` .2+<| `NEORV32_BUSKEEPER.CTRL` <|`0` _BUSKEEPER_ERR_TYPE_ ^| r/- <| Bus error type, valid if _BUSKEEPER_ERR_FLAG_
<|`31` _BUSKEEPER_ERR_FLAG_ ^| r/c <| Sticky error flag, clears after read or write access
.2+<| `0xffffff78` .2+<| `CTRL` <|`0` _BUSKEEPER_ERR_TYPE_ ^| r/- <| Bus error type, valid if _BUSKEEPER_ERR_FLAG_
<|`31` _BUSKEEPER_ERR_FLAG_ ^| r/c <| Sticky error flag, clears after read or write access
| `0xffffff7c` | - | _reserved_ | r/c | _reserved_ (mirrored access to `CTRL`)
|=======================

16
docs/datasheet/soc_cfs.adoc
View file

@ -57,8 +57,8 @@ register map table below). Note that all interface registers are declared as 32-
[source,c]
----
// C-code CFS usage example
NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
int temp = (int)NEORV32_CFS.REG[20]; // read from CFS register 20
NEORV32_CFS->REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
int temp = (int)NEORV32_CFS->REG[20]; // read from CFS register 20
----
[TIP]
@ -96,13 +96,13 @@ _IO_CFS_OUT_SIZE_ configuration generic (default = 32-bit). If the custom functi
**Register Map**
.CFS register map (`struct NEORV32_CFS`)
[cols="^4,<5,^2,^3,<14"]
[cols="^4,<2,^2,^2,<6"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xfffffe00` | `NEORV32_CFS.REG[0]` |`31:0` | (r)/(w) | custom CFS register 0
| `0xfffffe04` | `NEORV32_CFS.REG[1]` |`31:0` | (r)/(w) | custom CFS register 1
| ... | ... |`31:0` | (r)/(w) | ...
| `0xfffffef8` | `NEORV32_CFS.REG[62]` |`31:0` | (r)/(w) | custom CFS register 62
| `0xfffffefc` | `NEORV32_CFS.REG[63]` |`31:0` | (r)/(w) | custom CFS register 63
| `0xfffffe00` | `REG[0]` |`31:0` | (r)/(w) | custom CFS register 0
| `0xfffffe04` | `REG[1]` |`31:0` | (r)/(w) | custom CFS register 1
| ... | ... |`31:0` | (r)/(w) | ...
| `0xfffffef8` | `REG[62]` |`31:0` | (r)/(w) | custom CFS register 62
| `0xfffffefc` | `REG[63]` |`31:0` | (r)/(w) | custom CFS register 63
|=======================

10
docs/datasheet/soc_gpio.adoc
View file

@ -34,9 +34,9 @@ be performed within a single clock cycle.
[cols="<2,<2,^1,^1,<6"]
[options="header",grid="rows"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
| `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
| `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
| Address | Name [C] | Bit(s) | R/W | Function
| `0xffffffc0` | `INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
| `0xffffffc4` | `INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
| `0xffffffc8` | `OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
| `0xffffffcc` | `OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
|=======================

16
docs/datasheet/soc_gptmr.adoc
View file

@ -53,15 +53,15 @@ remains pending inside the CPU until it explicitly cleared by writing zero to th
**Register Map**
.GPTMR register map (`struct NEORV32_GPTMR`)
[cols="<2,<2,<4,^1,<7"]
[cols="<4,<2,<4,^1,<7"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.5+<| `0xffffff60` .5+<| `NEORV32_GPTMR.CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
| `0xffffff64` | `NEORV32_GPTMR.THRES` |`31:0` | r/w | Threshold value register
| `0xffffff68` | `NEORV32_GPTMR.COUNT` |`31:0` | r/w | Counter register
.5+<| `0xffffff60` .5+<| `CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
| `0xffffff64` | `THRES` |`31:0` | r/w | Threshold value register
| `0xffffff68` | `COUNT` |`31:0` | r/w | Counter register
|=======================

10
docs/datasheet/soc_mtime.adoc
View file

@ -38,9 +38,9 @@ can **NOT** be acknowledged by writing zero to the according <<_mip>> CSR bit. +
[cols="<3,<3,^1,^1,<6"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bits | R/W | Function
| `0xffffff90` | `NEORV32_MTIME.TIME_LO` | 31:0 | r/w | machine system time, low word
| `0xffffff94` | `NEORV32_MTIME.TIME_HI` | 31:0 | r/w | machine system time, high word
| `0xffffff98` | `NEORV32_MTIME.TIMECMP_LO` | 31:0 | r/w | time compare, low word
| `0xffffff9c` | `NEORV32_MTIME.TIMECMP_HI` | 31:0 | r/w | time compare, high word
| Address | Name [C] | Bits | R/W | Function
| `0xffffff90` | `TIME_LO` | 31:0 | r/w | machine system time, low word
| `0xffffff94` | `TIME_HI` | 31:0 | r/w | machine system time, high word
| `0xffffff98` | `TIMECMP_LO` | 31:0 | r/w | time compare, low word
| `0xffffff9c` | `TIMECMP_HI` | 31:0 | r/w | time compare, high word
|=======================

64
docs/datasheet/soc_neoled.adoc
View file

@ -188,39 +188,39 @@ will become pending if the FIFO (which is just a single register providing simpl
<<<
.NEOLED register map (`struct NEORV32_NEOLED`)
[cols="<4,<5,<9,^2,<9"]
[cols="<4,<2,<9,^2,<9"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.30+<| `0xffffffd8` .30+<| `NEORV32_NEOLED.CTRL` <|`0` _NEOLED_CTRL_EN_ ^| r/w <| NEOLED enable
<|`1` _NEOLED_CTRL_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
<|`2` _NEOLED_CTRL_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access
<|`3` _NEOLED_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0
<|`4` _NEOLED_CTRL_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1
<|`5` _NEOLED_CTRL_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2
<|`6` _NEOLED_CTRL_BUFS0_ ^| r/- .4+<| 4-bit log2(_IO_NEOLED_TX_FIFO_)
<|`7` _NEOLED_CTRL_BUFS1_ ^| r/-
<|`8` _NEOLED_CTRL_BUFS2_ ^| r/-
<|`9` _NEOLED_CTRL_BUFS3_ ^| r/-
<|`10` _NEOLED_CTRL_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~)
<|`11` _NEOLED_CTRL_T_TOT_1_ ^| r/w
<|`12` _NEOLED_CTRL_T_TOT_2_ ^| r/w
<|`13` _NEOLED_CTRL_T_TOT_3_ ^| r/w
<|`14` _NEOLED_CTRL_T_TOT_4_ ^| r/w
<|`15` _NEOLED_CTRL_T_ZERO_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a zero-bit (T~0H~)
<|`16` _NEOLED_CTRL_T_ZERO_H_1_ ^| r/w
<|`17` _NEOLED_CTRL_T_ZERO_H_2_ ^| r/w
<|`18` _NEOLED_CTRL_T_ZERO_H_3_ ^| r/w
<|`19` _NEOLED_CTRL_T_ZERO_H_4_ ^| r/w
<|`20` _NEOLED_CTRL_T_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~1H~)
<|`21` _NEOLED_CTRL_T_ONE_H_1_ ^| r/w
<|`22` _NEOLED_CTRL_T_ONE_H_2_ ^| r/w
<|`23` _NEOLED_CTRL_T_ONE_H_3_ ^| r/w
<|`24` _NEOLED_CTRL_T_ONE_H_4_ ^| r/w
<|`27` _NEOLED_CTRL_IRQ_CONF_ ^| r/w <| TX FIFO interrupt configuration: `0`=IRQ if FIFO is less than half-full, `1`=IRQ if FIFO is empty
<|`28` _NEOLED_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
<|`29` _NEOLED_CTRL_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full
<|`30` _NEOLED_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
<|`31` _NEOLED_CTRL_TX_BUSY_ ^| r/- <| TX serial engine is busy when set
| `0xffffffdc` | `NEORV32_NEOLED.DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit)
.30+<| `0xffffffd8` .30+<| `CTRL` <|`0` _NEOLED_CTRL_EN_ ^| r/w <| NEOLED enable
<|`1` _NEOLED_CTRL_MODE_ ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
<|`2` _NEOLED_CTRL_STROBE_ ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access
<|`3` _NEOLED_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler, bit 0
<|`4` _NEOLED_CTRL_PRSC1_ ^| r/w <| 3-bit clock prescaler, bit 1
<|`5` _NEOLED_CTRL_PRSC2_ ^| r/w <| 3-bit clock prescaler, bit 2
<|`6` _NEOLED_CTRL_BUFS0_ ^| r/- .4+<| 4-bit log2(_IO_NEOLED_TX_FIFO_)
<|`7` _NEOLED_CTRL_BUFS1_ ^| r/-
<|`8` _NEOLED_CTRL_BUFS2_ ^| r/-
<|`9` _NEOLED_CTRL_BUFS3_ ^| r/-
<|`10` _NEOLED_CTRL_T_TOT_0_ ^| r/w .5+<| 5-bit pulse clock ticks per total single-bit period (T~total~)
<|`11` _NEOLED_CTRL_T_TOT_1_ ^| r/w
<|`12` _NEOLED_CTRL_T_TOT_2_ ^| r/w
<|`13` _NEOLED_CTRL_T_TOT_3_ ^| r/w
<|`14` _NEOLED_CTRL_T_TOT_4_ ^| r/w
<|`15` _NEOLED_CTRL_T_ZERO_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a zero-bit (T~0H~)
<|`16` _NEOLED_CTRL_T_ZERO_H_1_ ^| r/w
<|`17` _NEOLED_CTRL_T_ZERO_H_2_ ^| r/w
<|`18` _NEOLED_CTRL_T_ZERO_H_3_ ^| r/w
<|`19` _NEOLED_CTRL_T_ZERO_H_4_ ^| r/w
<|`20` _NEOLED_CTRL_T_ONE_H_0_ ^| r/w .5+<| 5-bit pulse clock ticks per high-time for sending a one-bit (T~1H~)
<|`21` _NEOLED_CTRL_T_ONE_H_1_ ^| r/w
<|`22` _NEOLED_CTRL_T_ONE_H_2_ ^| r/w
<|`23` _NEOLED_CTRL_T_ONE_H_3_ ^| r/w
<|`24` _NEOLED_CTRL_T_ONE_H_4_ ^| r/w
<|`27` _NEOLED_CTRL_IRQ_CONF_ ^| r/w <| TX FIFO interrupt configuration: `0`=IRQ if FIFO is less than half-full, `1`=IRQ if FIFO is empty
<|`28` _NEOLED_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
<|`29` _NEOLED_CTRL_TX_HALF_ ^| r/- <| TX FIFO is _at least_ half full
<|`30` _NEOLED_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
<|`31` _NEOLED_CTRL_TX_BUSY_ ^| r/- <| TX serial engine is busy when set
| `0xffffffdc` | `DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32-/24-bit)
|=======================

24
docs/datasheet/soc_onewire.adoc
View file

@ -164,19 +164,19 @@ according <<_mip>> CSR FIRQ bit.
**Register Map**
.ONEWIRE register map (`struct NEORV32_ONEWIRE`)
[cols="<2,<2,<4,^1,<7"]
[cols="<4,<2,<6,^2,<6"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.10+<| `0xffffff70` .10+<| `NEORV32_ONEWIRE.CTRL` <|`0` _ONEWIRE_CTRL_EN_ ^| r/w <| ONEWIRE enable, reset if cleared
<|`2:1` _ONEWIRE_CTRL_PRSC1_ : _ONEWIRE_CTRL_PRSC0_ ^| r/w <| 2-bit clock prescaler select
<|`10:3` _ONEWIRE_CTRL_CLKDIV7_ : _ONEWIRE_CTRL_CLKDIV0_ ^| r/w <| 8-bit clock divider value
<|`11` _ONEWIRE_CTRL_TRIG_RST_ ^| -/w <| trigger reset pulse, auto-clears
<|`12` _ONEWIRE_CTRL_TRIG_BIT_ ^| -/w <| trigger single bit transmission, auto-clears
<|`13` _ONEWIRE_CTRL_TRIG_BYTE_ ^| -/w <| trigger full-byte transmission, auto-clears
<|`28:14` - ^| r/- <| _reserved_, read as zero
<|`29` _ONEWIRE_CTRL_SENSE_ ^| r/- <| current state of the bus line
<|`30` _ONEWIRE_CTRL_PRESENCE_ ^| r/- <| device presence detected after reset pulse
<|`31` _ONEWIRE_CTRL_BUSY_ ^| r/- <| operation in progress when set
| `0xffffff74` | `NEORV32_ONEWIRE.DATA` |`7:0` _ONEWIRE_DATA_MSB_ : _ONEWIRE_DATA_LSB_ | r/w | receive/transmit data (8-bit)
.10+<| `0xffffff70` .10+<| `CTRL` <|`0` _ONEWIRE_CTRL_EN_ ^| r/w <| ONEWIRE enable, reset if cleared
<|`2:1` _ONEWIRE_CTRL_PRSC1_ : _ONEWIRE_CTRL_PRSC0_ ^| r/w <| 2-bit clock prescaler select
<|`10:3` _ONEWIRE_CTRL_CLKDIV7_ : _ONEWIRE_CTRL_CLKDIV0_ ^| r/w <| 8-bit clock divider value
<|`11` _ONEWIRE_CTRL_TRIG_RST_ ^| -/w <| trigger reset pulse, auto-clears
<|`12` _ONEWIRE_CTRL_TRIG_BIT_ ^| -/w <| trigger single bit transmission, auto-clears
<|`13` _ONEWIRE_CTRL_TRIG_BYTE_ ^| -/w <| trigger full-byte transmission, auto-clears
<|`28:14` - ^| r/- <| _reserved_, read as zero
<|`29` _ONEWIRE_CTRL_SENSE_ ^| r/- <| current state of the bus line
<|`30` _ONEWIRE_CTRL_PRESENCE_ ^| r/- <| device presence detected after reset pulse
<|`31` _ONEWIRE_CTRL_BUSY_ ^| r/- <| operation in progress when set
| `0xffffff74` | `DATA` |`7:0` _ONEWIRE_DATA_MSB_ : _ONEWIRE_DATA_LSB_ | r/w | receive/transmit data (8-bit)
|=======================

34
docs/datasheet/soc_pwm.adoc
View file

@ -65,24 +65,24 @@ _**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`)
**Register Map**
.PWM register map (`struct neorv32_pwm_t`)
[cols="<4,<4,<6,^2,<8"]
[cols="<4,<2,<6,^2,<8"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.4+<| `0xffffff50` .4+<| `NEORV32_PWM.CTRL` <|`0` _PWM_CTRL_EN_ ^| r/w | PWM enable
<|`1` _PWM_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
<|`2` _PWM_CTRL_PRSC1_ ^| r/w
<|`3` _PWM_CTRL_PRSC2_ ^| r/w
.4+<| `0xffffff54` .4+<| `NEORV32_PWM.DC[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
.4+<| `0xffffff58` .4+<| `NEORV32_PWM.DC[1]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 4
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 5
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 6
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 7
.4+<| `0xffffff5c` .4+<| `NEORV32_PWM.DC[2]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 8
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 9
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 10
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 11
.4+<| `0xffffff50` .4+<| `CTRL` <|`0` _PWM_CTRL_EN_ ^| r/w | PWM enable
<|`1` _PWM_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
<|`2` _PWM_CTRL_PRSC1_ ^| r/w
<|`3` _PWM_CTRL_PRSC2_ ^| r/w
.4+<| `0xffffff54` .4+<| `DC[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
.4+<| `0xffffff58` .4+<| `DC[1]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 4
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 5
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 6
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 7
.4+<| `0xffffff5c` .4+<| `DC[2]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 8
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 9
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 10
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 11
|=======================

42
docs/datasheet/soc_sdi.adoc
View file

@ -60,38 +60,38 @@ clock domain to simplify timing behavior. However, the clock synchronization req
**SDI Interrupt**
The SDI module provides a set of interrupt conditions based on the level of the RX & TX FIFOs. The different
interrupt sources are enabled by the setting the control register's _SDI_CTRL_IRQ_ bits. All enabled interrupter
The SDI module provides a set of programmable interrupt conditions based on the level of the RX & TX FIFOs. The different
interrupt sources are enabled by setting the according control register's _SDI_CTRL_IRQ_ bits. All enabled interrupt
conditions are logically OR-ed so any enabled interrupt source will trigger the module's interrupt signal.
Once the SDI interrupt has fired it will remain active until the actual cause of the interrupt is resolved; for
example if just the _SDI_CTRL_IRQ_RX_AVAIL_ bit is set, the interrupt will keep firing until the RX FIFO is empty again.
Furthermore, an active SDI interrupt has to be explicitly cleared again by writing zero to the according
<<_mip>> CSR bit inside the SPI trap handler.
<<_mip>> CSR bit.
**Register Map**
.SDI register map (`struct NEORV32_SDI`)
[cols="<2,<2,<4,^1,<7"]
[cols="<2,<1,<4,^1,<7"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.16+<| `0xfffffff0` .16+<| `NEORV32_SDI.CTRL` <|`0` _SDI_CTRL_EN_ ^| r/w <| SDI module enable
<|`1` _SDI_CTRL_CLR_RX_ ^| -/w <| clear RX FIFO when set, bit auto-clears
<|`3:2` _reserved_ ^| r/- <| reserved, read as zero
<|`7:4` _SDI_CTRL_FIFO_MSB_ : _SDI_CTRL_FIFO_LSB_ ^| r/- <| FIFO depth; log2(_IO_SDI_FIFO_)
<|`14:8` _reserved_ ^| r/- <| reserved, read as zero
<|`15` _SDI_CTRL_IRQ_RX_AVAIL_ ^| r/w <| fire interrupt if RX FIFO is not empty
<|`16` _SDI_CTRL_IRQ_RX_HALF_ ^| r/w <| fire interrupt if RX FIFO is at least half full
<|`17` _SDI_CTRL_IRQ_RX_FULL_ ^| r/w <| fire interrupt if if RX FIFO is full
<|`18` _SDI_CTRL_IRQ_TX_EMPTY_ ^| r/w <| fire interrupt if TX FIFO is empty
<|`22:19` _reserved_ ^| r/- <| reserved, read as zero
<|`23` _SDI_CTRL_RX_AVAIL_ ^| r/- <| RX FIFO data available (RX FIFO not empty)
<|`24` _SDI_CTRL_RX_HALF_ ^| r/- <| RX FIFO at least half full
<|`25` _SDI_CTRL_RX_FULL_ ^| r/- <| RX FIFO full
<|`26` _SDI_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO empty
<|`27` _SDI_CTRL_TX_FULL_ ^| r/- <| TX FIFO full
<|`31:28` _reserved_ ^| r/- <| reserved, read as zero
| `0xfffffff4` | `NEORV32_SDI.DATA` |`7:0` | r/w | receive/transmit data (FIFO)
.16+<| `0xfffffff0` .16+<| `CTRL` <|`0` _SDI_CTRL_EN_ ^| r/w <| SDI module enable
<|`1` _SDI_CTRL_CLR_RX_ ^| -/w <| clear RX FIFO when set, bit auto-clears
<|`3:2` _reserved_ ^| r/- <| reserved, read as zero
<|`7:4` _SDI_CTRL_FIFO_MSB_ : _SDI_CTRL_FIFO_LSB_ ^| r/- <| FIFO depth; log2(_IO_SDI_FIFO_)
<|`14:8` _reserved_ ^| r/- <| reserved, read as zero
<|`15` _SDI_CTRL_IRQ_RX_AVAIL_ ^| r/w <| fire interrupt if RX FIFO is not empty
<|`16` _SDI_CTRL_IRQ_RX_HALF_ ^| r/w <| fire interrupt if RX FIFO is at least half full
<|`17` _SDI_CTRL_IRQ_RX_FULL_ ^| r/w <| fire interrupt if if RX FIFO is full
<|`18` _SDI_CTRL_IRQ_TX_EMPTY_ ^| r/w <| fire interrupt if TX FIFO is empty
<|`22:19` _reserved_ ^| r/- <| reserved, read as zero
<|`23` _SDI_CTRL_RX_AVAIL_ ^| r/- <| RX FIFO data available (RX FIFO not empty)
<|`24` _SDI_CTRL_RX_HALF_ ^| r/- <| RX FIFO at least half full
<|`25` _SDI_CTRL_RX_FULL_ ^| r/- <| RX FIFO full
<|`26` _SDI_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO empty
<|`27` _SDI_CTRL_TX_FULL_ ^| r/- <| TX FIFO full
<|`31:28` _reserved_ ^| r/- <| reserved, read as zero
| `0xfffffff4` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
|=======================

18
docs/datasheet/soc_sysinfo.adoc
View file

@ -29,18 +29,18 @@ will signal a "DEVICE ERROR" in this case.
**Register Map**
.SYSINFO register map (`struct NEORV32_SYSINFO`)
[cols="<2,<4,<7"]
[cols="<2,<2,<6"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Function
| `0xffffffe0` | `NEORV32_SYSINFO.CLK` | clock speed in Hz (via top's <<_clock_frequency>> generic)
| `0xffffffe4` | `NEORV32_SYSINFO.CUSTOM_ID | custom user-defined ID (via top's <<_custom_id>> generic)
| `0xffffffe8` | `NEORV32_SYSINFO.SOC` | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xffffffec` | `NEORV32_SYSINFO.CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffff0` | `NEORV32_SYSINFO.ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
| `0xfffffff4` | `NEORV32_SYSINFO.IMEM_SIZE` | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic)
| `0xfffffff8` | `NEORV32_SYSINFO.DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
| `0xfffffffc` | `NEORV32_SYSINFO.DMEM_SIZE` | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic)
| `0xffffffe0` | `CLK` | clock speed in Hz (via top's <<_clock_frequency>> generic)
| `0xffffffe4` | `CUSTOM_ID | custom user-defined ID (via top's <<_custom_id>> generic)
| `0xffffffe8` | `SOC` | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xffffffec` | `CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffff0` | `ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
| `0xfffffff4` | `IMEM_SIZE` | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic)
| `0xfffffff8` | `DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
| `0xfffffffc` | `DMEM_SIZE` | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic)
|=======================

12
docs/datasheet/soc_trng.adoc
View file

@ -70,13 +70,13 @@ setting the _TRNG_CTRL_FIFO_CLR_ flag. Note that this flag is write-only and aut
**Register Map**
.TRNG register map (`struct NEORV32_TRNG`)
[cols="<2,<2,<4,^1,<7"]
[cols="<2,<1,<4,^1,<7"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.5+<| `0xffffffb8` .5+<| `NEORV32_TRNG.CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data
<|`28` _TRNG_CTRL_FIFO_CLR_ ^| -/w <| flush random data FIFO when set (auto clears)
<|`29` _TRNG_CTRL_SIM_MODE_ ^| r/- <| simulation mode (PRNG!)
<|`30` _TRNG_CTRL_EN_ ^| r/w <| TRNG enable
<|`31` _TRNG_CTRL_VALID_ ^| r/- <| random data is valid when set
.5+<| `0xffffffb8` .5+<| `CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data
<|`28` _TRNG_CTRL_FIFO_CLR_ ^| -/w <| flush random data FIFO when set (auto clears)
<|`29` _TRNG_CTRL_SIM_MODE_ ^| r/- <| simulation mode (PRNG!)
<|`30` _TRNG_CTRL_EN_ ^| r/w <| TRNG enable
<|`31` _TRNG_CTRL_VALID_ ^| r/- <| random data is valid when set
|=======================

26
docs/datasheet/soc_twi.adoc
View file

@ -127,20 +127,20 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
**Register Map**
.TWI register map (`struct NEORV32_TWI`)
[cols="<2,<2,<4,^1,<7"]
[cols="<2,<1,<4,^1,<7"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.10+<| `0xffffffb0` .10+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable, reset if cleared
<|`1` _TWI_CTRL_START_ ^| -/w <| generate START condition, auto-clears
<|`2` _TWI_CTRL_STOP_ ^| -/w <| generate STOP condition, auto-clears
<|`3` _TWI_CTRL_MACK_ ^| r/w <| generate controller-ACK for each transmission ("MACK")
<|`4` _TWI_CTRL_CSEN_ ^| r/w <| allow clock stretching when set
<|`7:5` _TWI_CTRL_PRSC2_ : _TWI_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler select
<|`11:8` _TWI_CTRL_CDIV3_ : _TWI_CTRL_CDIV0_ ^| r/w <| 4-bit clock divider
<|`28:12` - ^| r/- <| _reserved_, read as zero
<|`29` _TWI_CTRL_CLAIMED_ ^| r/- <| set if the TWI bus is claimed by any controller
<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set, NACK received when cleared
<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : _TWI_DATA_LSB_ | r/w | receive/transmit data
.10+<| `0xffffffb0` .10+<| `CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable, reset if cleared
<|`1` _TWI_CTRL_START_ ^| -/w <| generate START condition, auto-clears
<|`2` _TWI_CTRL_STOP_ ^| -/w <| generate STOP condition, auto-clears
<|`3` _TWI_CTRL_MACK_ ^| r/w <| generate controller-ACK for each transmission ("MACK")
<|`4` _TWI_CTRL_CSEN_ ^| r/w <| allow clock stretching when set
<|`7:5` _TWI_CTRL_PRSC2_ : _TWI_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler select
<|`11:8` _TWI_CTRL_CDIV3_ : _TWI_CTRL_CDIV0_ ^| r/w <| 4-bit clock divider
<|`28:12` - ^| r/- <| _reserved_, read as zero
<|`29` _TWI_CTRL_CLAIMED_ ^| r/- <| set if the TWI bus is claimed by any controller
<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set, NACK received when cleared
<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
| `0xffffffb4` | `DATA` |`7:0` _TWI_DATA_MSB_ : _TWI_DATA_LSB_ | r/w | receive/transmit data
|=======================

62
docs/datasheet/soc_uart.adoc
View file

@ -161,37 +161,37 @@ section https://stnolting.github.io/neorv32/ug/#_simulating_the_processor[Simula
**Register Map**
.UART0 register map (`struct NEORV32_UART0`)
[cols="<3,<3,<4,^1,<4"]
[cols="<4,<2,<5,^2,<5"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.21+<| `0xffffffa0` .21+<| `NEORV32_UART0.CTRL` <|`11:0` _UART_CTRL_BAUDxx_ ^| r/w <| 12-bit Baud value configuration value
<|`12` _UART_CTRL_SIM_MODE_ ^| r/w <| enable **simulation mode**
<|`13` _UART_CTRL_RX_EMPTY_ ^| r/- <| RX FIFO is empty
<|`14` _UART_CTRL_RX_HALF_ ^| r/- <| RX FIFO is at least half-full
<|`15` _UART_CTRL_RX_FULL_ ^| r/- <| RX FIFO is full
<|`16` _UART_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
<|`17` _UART_CTRL_TX_HALF_ ^| r/- <| TX FIFO is at least half-full
<|`18` _UART_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
<|`19` - ^| r/- <| _reserved_, read as zero
<|`20` _UART_CTRL_RTS_EN_ ^| r/w <| enable RTS hardware flow control
<|`21` _UART_CTRL_CTS_EN_ ^| r/w <| enable CTS hardware flow control
<|`22` _UART_CTRL_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)
<|`23` _UART_CTRL_PMODE1_ ^| r/w
<|`24` _UART_CTRL_PRSC0_ ^| r/w .3+<| 3-bit Baud rate clock prescaler select
<|`25` _UART_CTRL_PRSC1_ ^| r/w
<|`26` _UART_CTRL_PRSC2_ ^| r/w
<|`27` _UART_CTRL_CTS_ ^| r/- <| current state of UART's CTS input signal
<|`28` _UART_CTRL_EN_ ^| r/w <| UART enable
<|`29` _UART_CTRL_RX_IRQ_ ^| r/w <| RX IRQ mode: `1`=FIFO at least half-full; `0`=FIFO not empty
<|`30` _UART_CTRL_TX_IRQ_ ^| r/w <| TX IRQ mode: `1`=FIFO less than half-full; `0`=FIFO not full
<|`31` _UART_CTRL_TX_BUSY_ ^| r/- <| transmitter busy flag
.6+<| `0xffffffa4` .6+<| `NEORV32_UART0.DATA` <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit)
<|`31:0` - ^| -/w <| **simulation data output**
<|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error
<|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit not set)
<|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun
<|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set
.21+<| `0xffffffa0` .21+<| `CTRL` <|`11:0` _UART_CTRL_BAUDxx_ ^| r/w <| 12-bit Baud value configuration value
<|`12` _UART_CTRL_SIM_MODE_ ^| r/w <| enable **simulation mode**
<|`13` _UART_CTRL_RX_EMPTY_ ^| r/- <| RX FIFO is empty
<|`14` _UART_CTRL_RX_HALF_ ^| r/- <| RX FIFO is at least half-full
<|`15` _UART_CTRL_RX_FULL_ ^| r/- <| RX FIFO is full
<|`16` _UART_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO is empty
<|`17` _UART_CTRL_TX_HALF_ ^| r/- <| TX FIFO is at least half-full
<|`18` _UART_CTRL_TX_FULL_ ^| r/- <| TX FIFO is full
<|`19` - ^| r/- <| _reserved_, read as zero
<|`20` _UART_CTRL_RTS_EN_ ^| r/w <| enable RTS hardware flow control
<|`21` _UART_CTRL_CTS_EN_ ^| r/w <| enable CTS hardware flow control
<|`22` _UART_CTRL_PMODE0_ ^| r/w .2+<| parity bit enable and configuration (`00`/`01`= no parity; `10`=even parity; `11`=odd parity)
<|`23` _UART_CTRL_PMODE1_ ^| r/w
<|`24` _UART_CTRL_PRSC0_ ^| r/w .3+<| 3-bit Baud rate clock prescaler select
<|`25` _UART_CTRL_PRSC1_ ^| r/w
<|`26` _UART_CTRL_PRSC2_ ^| r/w
<|`27` _UART_CTRL_CTS_ ^| r/- <| current state of UART's CTS input signal
<|`28` _UART_CTRL_EN_ ^| r/w <| UART enable
<|`29` _UART_CTRL_RX_IRQ_ ^| r/w <| RX IRQ mode: `1`=FIFO at least half-full; `0`=FIFO not empty
<|`30` _UART_CTRL_TX_IRQ_ ^| r/w <| TX IRQ mode: `1`=FIFO less than half-full; `0`=FIFO not full
<|`31` _UART_CTRL_TX_BUSY_ ^| r/- <| transmitter busy flag
.6+<| `0xffffffa4` .6+<| `DATA` <|`7:0` _UART_DATA_MSB_ : _UART_DATA_LSB_ ^| r/w <| receive/transmit data (8-bit)
<|`31:0` - ^| -/w <| **simulation data output**
<|`28` _UART_DATA_PERR_ ^| r/- <| RX parity error
<|`29` _UART_DATA_FERR_ ^| r/- <| RX data frame error (stop bit not set)
<|`30` _UART_DATA_OVERR_ ^| r/- <| RX data overrun
<|`31` _UART_DATA_AVAIL_ ^| r/- <| RX data available when set
|=======================
@ -238,10 +238,10 @@ data words.
**Register Map**
.UART1 register map (`struct NEORV32_UART1`)
[cols="<3,<3,<4,^1,<4"]
[cols="<2,<1,<1,^1,<2"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
| `0xffffffd0` | `NEORV32_UART1.CTRL` | ... | ... | Same as UART0
| `0xffffffd4` | `NEORV32_UART1.DATA` | ... | ... | Same as UART0
| `0xffffffd0` | `CTRL` | ... | ... | Same as UART0
| `0xffffffd4` | `DATA` | ... | ... | Same as UART0
|=======================

18
docs/datasheet/soc_wdt.adoc
View file

@ -78,16 +78,16 @@ the last system reset was caused by the watchdog itself.
**Register Map**
.WDT register map (`struct NEORV32_WDT`)
[cols="<2,<2,<4,^1,^1,^2,<4"]
[cols="<2,<1,<4,^1,^1,^2,<4"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function
.8+<| `0xffffffbc` .8+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
<|`1 _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already
<|`2` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode
<|`3` _WDT_CTRL_SEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode
<|`4` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| reset watchdog when set, auto-clears
<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
<|`7:6` - ^| r/- ^| - ^| - <| _reserved_, reads as zero
<|`31:8` _WDT_CTRL_TIMEOUT_MSB_ : _WDT_CTRL_TIMEOUT_LSB_ ^| r/w ^| 0 ^| no <| 24-bit watchdog timeout value
.8+<| `0xffffffbc` .8+<| `CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
<|`1 _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already
<|`2` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode
<|`3` _WDT_CTRL_SEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode
<|`4` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| reset watchdog when set, auto-clears
<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
<|`7:6` - ^| r/- ^| - ^| - <| _reserved_, reads as zero
<|`31:8` _WDT_CTRL_TIMEOUT_MSB_ : _WDT_CTRL_TIMEOUT_LSB_ ^| r/w ^| 0 ^| no <| 24-bit watchdog timeout value
|=======================

42
docs/datasheet/soc_xip.adoc
View file

@ -198,28 +198,28 @@ By using the XIP burst mode flash read accesses can be accelerated by up to 50%.
**Register Map**
.XIP Register Map (`struct NEORV32_XIP`)
[cols="<2,<2,<4,^1,<7"]
[cols="<2,<1,<4,^1,<7"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.17+<| `0xffffff40` .17+<| `NEORV32_XIP.CTRL` <|`0` _XIP_CTRL_EN_ ^| r/w <| XIP module enable
<|`1` _XIP_CTRL_PRSC0_ ^| r/w .3+| 3-bit SPI clock prescaler select
<|`2` _XIP_CTRL_PRSC1_ ^| r/w
<|`3` _XIP_CTRL_PRSC2_ ^| r/w
<|`4` _XIP_CTRL_CPOL_ ^| r/w <| SPI clock polarity
<|`5` _XIP_CTRL_CPHA_ ^| r/w <| SPI clock phase
<|`9:6` _XIP_CTRL_SPI_NBYTES_MSB_ : _XIP_CTRL_SPI_NBYTES_LSB_ ^| r/w <| Number of bytes in SPI transaction (1..9)
<|`10` _XIP_CTRL_XIP_EN_ ^| r/w <| XIP mode enable
<|`12:11` _XIP_CTRL_XIP_ABYTES_MSB_ : _XIP_CTRL_XIP_ABYTES_LSB_ ^| r/w <| Number of address bytes for XIP flash (minus 1)
<|`20:13` _XIP_CTRL_RD_CMD_MSB_ : _XIP_CTRL_RD_CMD_LSB_ ^| r/w <| Flash read command
<|`24:21` _XIP_CTRL_XIP_PAGE_MSB_ : _XIP_CTRL_XIP_PAGE_LSB_ ^| r/w <| XIP memory page
<|`25` _XIP_CTRL_SPI_CSEN_ ^| r/w <| Allow SPI chip-select to be actually asserted when set
<|`26` _XIP_CTRL_HIGHSPEED_ ^| r/w <| enable SPI high-speed mode (ignoring _XIP_CTRL_PRSC_)
<|`27` _XIP_CTRL_BURST_EN_ ^| r/w <| Enable XIP burst mode
<|`29:28` ^| r/- <| _reserved_, read as zero
<|`30` _XIP_CTRL_PHY_BUSY_ ^| r/- <| SPI PHY busy when set
<|`31` _XIP_CTRL_XIP_BUSY_ ^| r/- <| XIP access in progress when set
| `0xffffff44` | _reserved_ |`31:0` | r/- | _reserved_, read as zero
| `0xffffff48` | `NEORV32_XIP.DATA_LO` |`31:0` | r/w | Direct SPI access - data register low
| `0xffffff4C` | `NEORV32_XIP.DATA_HI` |`31:0` | -/w | Direct SPI access - data register high; write access triggers SPI transfer
.17+<| `0xffffff40` .17+<| `CTRL` <|`0` _XIP_CTRL_EN_ ^| r/w <| XIP module enable
<|`1` _XIP_CTRL_PRSC0_ ^| r/w .3+| 3-bit SPI clock prescaler select
<|`2` _XIP_CTRL_PRSC1_ ^| r/w
<|`3` _XIP_CTRL_PRSC2_ ^| r/w
<|`4` _XIP_CTRL_CPOL_ ^| r/w <| SPI clock polarity
<|`5` _XIP_CTRL_CPHA_ ^| r/w <| SPI clock phase
<|`9:6` _XIP_CTRL_SPI_NBYTES_MSB_ : _XIP_CTRL_SPI_NBYTES_LSB_ ^| r/w <| Number of bytes in SPI transaction (1..9)
<|`10` _XIP_CTRL_XIP_EN_ ^| r/w <| XIP mode enable
<|`12:11` _XIP_CTRL_XIP_ABYTES_MSB_ : _XIP_CTRL_XIP_ABYTES_LSB_ ^| r/w <| Number of address bytes for XIP flash (minus 1)
<|`20:13` _XIP_CTRL_RD_CMD_MSB_ : _XIP_CTRL_RD_CMD_LSB_ ^| r/w <| Flash read command
<|`24:21` _XIP_CTRL_XIP_PAGE_MSB_ : _XIP_CTRL_XIP_PAGE_LSB_ ^| r/w <| XIP memory page
<|`25` _XIP_CTRL_SPI_CSEN_ ^| r/w <| Allow SPI chip-select to be actually asserted when set
<|`26` _XIP_CTRL_HIGHSPEED_ ^| r/w <| enable SPI high-speed mode (ignoring _XIP_CTRL_PRSC_)
<|`27` _XIP_CTRL_BURST_EN_ ^| r/w <| Enable XIP burst mode
<|`29:28` ^| r/- <| _reserved_, read as zero
<|`30` _XIP_CTRL_PHY_BUSY_ ^| r/- <| SPI PHY busy when set
<|`31` _XIP_CTRL_XIP_BUSY_ ^| r/- <| XIP access in progress when set
| `0xffffff44` | _reserved_ |`31:0` | r/- | _reserved_, read as zero
| `0xffffff48` | `DATA_LO` |`31:0` | r/w | Direct SPI access - data register low
| `0xffffff4C` | `DATA_HI` |`31:0` | -/w | Direct SPI access - data register high; write access triggers SPI transfer
|=======================

10
docs/datasheet/soc_xirq.adoc
View file

@ -75,12 +75,12 @@ XIRQ_TRIGGER_POLARITY => x"ffffffff";
**Register Map**
.XIRQ register map (`struct NEORV32_XIRQ`)
[cols="^4,<5,^2,^2,<14"]
[cols="^4,<2,^2,^2,<14"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xffffff80` | `NEORV32_XIRQ.IER` | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned)
| `0xffffff84` | `NEORV32_XIRQ.IPR` | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears according pending interrupt
| `0xffffff88` | `NEORV32_XIRQ.SCR` | `4:0` | r/w | Channel id (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current interrupt
| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero
| `0xffffff80` | `IER` | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned)
| `0xffffff84` | `IPR` | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears according pending interrupt
| `0xffffff88` | `SCR` | `4:0` | r/w | Channel id (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current interrupt
| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero
|=======================