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updates due to new rte functions

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stnolting 2020-07-05 22:24:26 +02:00
parent b31a77ecad
commit fa01809f60
1 changed files with 10 additions and 4 deletions
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14
sw/example/cpu_test/main.c
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@ -51,7 +51,7 @@
//** Set 1 for detailed exception debug information */
#define DETAILED_EXCEPTION_DEBUG 0
//** Reachable unaligned address */
#define ADDR_UNALIGNED 0x00000001
#define ADDR_UNALIGNED 0x00000002
//** Unreachable aligned address */
#define ADDR_UNREACHABLE 0xFFFFFF00
/**@}*/
@ -144,7 +144,7 @@ int main() {
neorv32_mtime_set_timecmp(mtime_cmp_max);
// intro
neorv32_uart_printf("\n\n------ CPU TEST ------n\n");
neorv32_uart_printf("\n\n------ CPU TEST ------\n\n");
// show full HW config report
neorv32_rte_print_hw_config();
@ -202,6 +202,9 @@ int main() {
neorv32_uart_printf("EXC I_ALIGN: ");
cnt_test++;
// disable C mode
neorv32_cpu_csr_write(CSR_MISA, neorv32_cpu_csr_read(CSR_MISA) & (~(1<<CPU_MISA_C_EXT)));
// call unaligned address
((void (*)(void))ADDR_UNALIGNED)();
@ -217,6 +220,9 @@ int main() {
exception_handler_answer = 0;
#endif
// re-enable C mode
neorv32_cpu_csr_write(CSR_MISA, neorv32_cpu_csr_read(CSR_MISA) | (1<<CPU_MISA_C_EXT));
// ----------------------------------------------------------
// Instruction access fault
@ -296,7 +302,7 @@ int main() {
cnt_test++;
// load from unaligned address
asm volatile ("lh zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
asm volatile ("lw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_L_MISALIGN) {
@ -340,7 +346,7 @@ int main() {
cnt_test++;
// store to unaligned address
asm volatile ("sh zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
asm volatile ("sw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED));
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == ANSWER_S_MISALIGN) {