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[crt0] re-initi mstatus & fix trap cause identification

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always emit 32-bit code for crt0
This commit is contained in:
stnolting 2023-12-11 21:46:51 +01:00
parent 9adce675f1
commit fcdfeb9e63
1 changed files with 11 additions and 16 deletions
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27
sw/common/crt0.S
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@ -35,6 +35,7 @@
.file "crt0.S"
.section .text.crt0
.balign 4
.option norvc // only 32-bit instructions
.global _start
.global __crt0_entry
.global __crt0_main_exit
@ -44,22 +45,15 @@ __crt0_entry:
.cfi_startproc
.cfi_undefined ra
// ************************************************************************************************
// We need to ensure interrupts are completely disabled at start. This is required if this code
// is part of a program uploaded by the on-chip debugger (potentionally taking over control from the
// bootloader). We setup a new stack pointer here and WE DO NOT WANT TO trap to an outdated trap
// handler with a modified stack pointer.
// ************************************************************************************************
csrrwi zero, mstatus, 0 // clear mstatus; disable machine-level interrupts
// ************************************************************************************************
// Setup CPU core CSRs
// ************************************************************************************************
__crt0_cpu_csr_init:
la x1, __crt0_trap_handler // configure early-boot trap handler
csrw mtvec, x1
csrw mie, zero // disable all interrupt sources
li x1, 0x00001800
csrw mstatus, x1 // reset mstatus (e.g. no interrupt in machine-mode)
la x1, __crt0_trap_handler // configure early-boot trap handler
csrw mtvec, x1
csrw mie, zero // disable all interrupt sources
// ************************************************************************************************
@ -228,17 +222,18 @@ __crt0_trap_handler:
// backup x8
csrw mscratch, x8
// we are done if interrupt
// exit if interrupt
csrr x8, mcause
bltz x8, __crt0_trap_handler_end
srli x8, x8, 31 // isolate MSB (set for interrupts)
bnez x8, __crt0_trap_handler_end
// mepc = mepc + 2 (for compressed instruction)
csrr x8, mepc
addi x8, x8, +2
csrw mepc, x8
// we are done if trap-causing instruction is compressed
csrr x8, mtinst // get transformed trap-causing instruction
// exit if exception-causing instruction is compressed
csrr x8, mtinst // get transformed exception-causing instruction
andi x8, x8, 3 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
addi x8, x8, -3 // x8 is zero after this if uncompressed instruction
beqz x8, __crt0_trap_handler_end