17 commits

Author	SHA1	Message	Date
stnolting	5af13b2c3b	[docs/references] clean-up RISC-V Zicond specs.	2024-01-08 15:31:50 +01:00
stnolting	58f58f9b8f	[docs/references] add Zicond spec	2023-12-01 21:39:05 +01:00
stnolting	737b99ca8b	[docs/references] upgrade debug spec. ... upgrade Sdtrig to v1.0	2023-11-30 17:24:59 +01:00
stnolting	f0a047886c	[docs] add RISC-V SMCNTRPMF spec.	2023-09-15 20:37:17 +02:00
stnolting	ac0c8f1ace	[docs] update RISC-V reference specs.	2023-04-22 21:53:01 +02:00
stnolting	5728789113	[docs] update Zicond ISA spec	2023-03-11 09:34:11 +01:00
stnolting	ddf7c0b1a5	[docs/references] add Zicond ISA spec	2023-02-23 18:28:04 +01:00
stnolting	c8f8ae2cc7	[docs/references] upgrade debug spec	2022-12-22 17:50:30 +01:00
stnolting	5dacd0fbc4	[docs] update RISC-V specs.	2022-06-22 20:23:36 +02:00
stnolting	1dc3624045	📚 update RISC-V specs. ... Machine ISA v1.12 (ratified)	2022-03-04 20:26:17 +01:00
stnolting	f7abb2226f	[docs/references] upadted RISC-V specs.	2021-10-30 01:17:07 +02:00
stnolting	bd3acc4105	[docs] updated RISC-V specs.	2021-09-11 07:28:38 +02:00
stnolting	46587fe697	[docs] updated B extension spec	2021-09-08 17:08:04 +02:00
stnolting	f2e69a36b3	✨ [docs] added RISC-V "Zmmul" ISA extensions ... * implement mltiplication instructions only (no division instructions) * sub-extensions of M extensions * for size-constrained setups; requires ~50% less hardware than M extensions * div[u] and rem[u] instructions will raise an illegal instruction exception	2021-06-24 15:58:16 +02:00
umarcor	5d3d00272f	[docs] move bitmanip-draft.pdf into references	2021-05-22 20:38:22 +02:00
stnolting	ab8e651c51	[docs/reference] added RISC-V debug spec ... ✨ for upcoming NEORV32 *on-chip debugger* 😉	2021-05-19 18:07:15 +02:00
umarcor	87b4777b96	docs: create subdir 'references'	2021-05-18 04:43:17 +02:00