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64 lines
3.4 KiB
Text
64 lines
3.4 KiB
Text
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==== Core Local Interruptor (CLINT)
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[cols="<3,<3,<4"]
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[grid="none"]
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|=======================
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| Hardware source files: | neorv32_clint.vhd |
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| Software driver files: | neorv32_clint.c | link:https://stnolting.github.io/neorv32/sw/neorv32__clint_8c.html[Online software reference (Doxygen)]
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| | neorv32_clint.h | link:https://stnolting.github.io/neorv32/sw/neorv32__clint_8h.html[Online software reference (Doxygen)]
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| Top entity ports: | `mtime_irq_i` | RISC-V machine timer IRQ if CLINT is **not** implemented
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| | `msw_irq_i` | RISC-V software IRQ if CLINT is **not** implemented
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| | `mtime_time_o` | Current system time (from CLINT's MTIMER)
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| Configuration generics: | `IO_CLINT_EN` | implement core local interruptor when `true`
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| CPU interrupts: | `MTI` | machine timer interrupt (see <<_processor_interrupts>>)
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| | `MSI` | machine software interrupt (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The core local interruptor provides machine-level timer and software interrupts for a set of CPU cores (also called _harts).
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It is compatible to the original SiFive(R) CLINT specifications and it is also backwards-compatible to the upcoming RISC-V
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_Advanced Core Local Interruptor (ACLINT)_ specifications. In terms of the ACLINT spec the NEORV32 CLINT implements three
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_devices_ that are placed next to each other in the address space: an MTIMER and an MSWI device.
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The CLINT can support up to 4095 harts. However, the NEORV32 CLINT is configured for a single hart only (yet).
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Hence, only the according registers are implemented while the remaining ones are hardwired to zero.
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**MTIMER Device**
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The MTIMER device provides a global 64-bit machine timer (`NEORV32_CLINT->MTIME`) that increments with every main processor
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clock tick. Upon reset the timer is reset to all zero. Each hart provides an individual 64-bit timer-compare register
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(`NEORV32_CLINT->MTIMECMP[0]` for hart 0). Whenever `MTIMECMP >= MTIME` the according machine timer interrupt is pending.
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**MSIW Device**
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The MSIV provides software interrupts for each hart via hart-individual memory-mapped registers (`NEORV32_CLINT->MSWI[0]` for
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hart 0). Setting bit 0 of this register will bring the machine software interrupt into pending state.
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.External Machine Timer and Software Interrupts
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[NOTE]
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If the NEORV32 CLINT module is disabled (`IO_CLINT_EN` = `false`) the core's machine timer interrupt and
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machine software interrupt become available as processor-external signals (`mtime_irq_i` and `msw_irq_i`, respectively).
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**Register Map**
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.CLINT register map (`struct NEORV32_CLINT`)
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[cols="<3,<3,^1,^1,<6"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bits | R/W | Function
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.2+<| `0xfff40000` .2+<| `MSWI[0]` ^| 0 ^| r/w <| trigger machine software interrupt for hart 0 when set
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^| 31:1 ^| r/- <| hardwired to zero
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.2+<| `0xfff40004` .2+<| `MSWI[1]` ^| 0 ^| r/w <| trigger machine software interrupt for hart 1 when set
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^| 31:1 ^| r/- <| hardwired to zero
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| `0xfff44000` | `MTIMECMP[0]` | 63:0 | r/w | 64-bit time compare for hart 0
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| `0xfff44008` | `MTIMECMP[1]` | 63:0 | r/w | 64-bit time compare for hart 1
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| `0xfff4bff8` | `MTIME` | 63:0 | r/w | 64-bit global machine timer
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|=======================
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