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67 lines
3.4 KiB
Text
67 lines
3.4 KiB
Text
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==== General Purpose Timer (GPTMR)
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|=======================
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| Hardware source files: | neorv32_gptmr.vhd |
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| Software driver files: | neorv32_gptmr.c | link:https://stnolting.github.io/neorv32/sw/neorv32__gptmr_8c.html[Online software reference (Doxygen)]
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| | neorv32_gptmr.h | link:https://stnolting.github.io/neorv32/sw/neorv32__gptmr_8h.html[Online software reference (Doxygen)]
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| Top entity ports: | none |
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| Configuration generics: | `IO_GPTMR_EN` | implement general purpose timer when `true`
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| CPU interrupts: | fast IRQ channel 12 | timer interrupt (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The general purpose timer module implements a simple 32-bit interval timer. It is implemented if the processor's
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`IO_GPTMR_EN` top generic is set `true`. The timer provides a pre-scaled counter register that can trigger an interrupt
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when reaching a programmable threshold value.
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The GPTMR provides three interface registers : a control register (`CTRL`), a 32-bit counter register (`COUNT`) and a
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32-bit threshold register (`THRES`). The timer is globally enabled by setting the `GPTMR_CTRL_EN` bit in the module's
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control register. When the timer is enabled the `COUNT` register will start incrementing from zero at a programmable
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rate that scales the main processor clock. this pre-scaler is configured via the three `GPTMR_CTRL_PRSCx`
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control register bits:
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.GPTMR prescaler configuration
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|=======================
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| **`GPTMR_CTRL_PRSC[2:0]`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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Whenever the counter register `COUNT` equals the programmable threshold value `THRES` the module's interrupt signal becomes
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pending (indicated by `GPTMR_CTRL_IRQ_PND` being set). In this case the `COUNT` register is automatically reset and restarts
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incrementing from zero. Note that a pending interrupt has to be cleared manually by writing a `1` to `GPTMR_CTRL_IRQ_CLR`.
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.Resetting the Counter
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[NOTE]
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Disabling the GPTMR will also clear the `COUNT` register.
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**Interrupt**
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The GPTRM provides a single interrupt line is triggered whenever `COUNT` equals `THRES`. Once triggered, the interrupt will
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stay pending until explicitly cleared by writing a 1 to `GPTMR_CTRL_IRQ_CLR`.
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**Register Map**
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.GPTMR register map (`struct NEORV32_GPTMR`)
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.5+<| `0xfff10000` .5+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
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<|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
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<|`29:4` - ^| r/- <| _reserved_, read as zero
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<|`30` `GPTMR_CTRL_IRQ_CLR` ^| -/w <| Write `1` to clear timer-match interrupt; auto-clears
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<|`31` `GPTMR_CTRL_IRQ_PND` ^| r/- <| Timer-match interrupt pending
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| `0xfff10004` | `THRES` |`31:0` | r/w | Threshold value register
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| `0xfff10008` | `COUNT` |`31:0` | r/- | Counter register
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|=======================
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