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72 lines
3.9 KiB
Text
72 lines
3.9 KiB
Text
<<<
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:sectnums:
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==== True Random-Number Generator (TRNG)
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[cols="<3,<3,<4"]
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[grid="none"]
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|=======================
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| Hardware source files: | neorv32_trng.vhd |
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| Software driver files: | neorv32_trng.c | link:https://stnolting.github.io/neorv32/sw/neorv32__trng_8c.html[Online software reference (Doxygen)]
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| | neorv32_trng.h | link:https://stnolting.github.io/neorv32/sw/neorv32__trng_8h.html[Online software reference (Doxygen)]
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| Top entity ports: | none |
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| Configuration generics: | `IO_TRNG_EN` | implement TRNG when `true`
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| | `IO_TRNG_FIFO` | data FIFO depth, min 1, has to be a power of two
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| CPU interrupts: | none
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|=======================
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**Overview**
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The NEORV32 true random number generator provides _physically_ true random numbers. It is based on free-running
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ring-oscillators that generate **phase noise** when being sampled by a constant clock. This phase noise is
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used as physical entropy source. The TRNG features a platform independent architecture without FPGA-specific
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primitives, macros or attributes so it can be synthesized for _any_ FPGA.
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.In-Depth Documentation
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[TIP]
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For more information about the neoTRNG architecture and an analysis of its random quality check out the
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neoTRNG repository: https://github.com/stnolting/neoTRNG
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.Inferring Latches
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[NOTE]
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The synthesis tool might emit warnings regarding **inferred latches** or **combinatorial loops**. However, this
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is not design flaw as this is exactly what we want. ;)
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**Theory of Operation**
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The TRNG provides two memory mapped interface register. One control register (`CTRL`) for configuration and
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status check and one data register (`DATA`) for obtaining the random data. The TRNG is enabled by setting the
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control register's `TRNG_CTRL_EN`. As soon as the `TRNG_CTRL_AVAIL` bit is set a new random data byte is
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available and can be obtained from the lowest 8 bits of the `DATA` register. If this bit is cleared, there
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is no valid data available and the reading `DATA` will return all-zero.
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An internal entropy FIFO can be configured using the `IO_TRNG_FIFO` generic. This FIFO automatically samples
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new random data from the TRNG to provide some kind of _random data pool_ for applications which require a
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larger number of random data in a short time. The random data FIFO can be cleared at any time either by
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disabling the TRNG or by setting the `TRNG_CTRL_FIFO_CLR` flag. The FIFO depth can be retrieved by software
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via the `TRNG_CTRL_FIFO_*` bits.
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.Simulation
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[IMPORTANT]
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When simulating the processor the TRNG is automatically set to "simulation mode". In this mode the physical
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entropy sources (the ring oscillators) are replaced by a simple **pseudo RNG** based on a LFSR providing only
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**deterministic pseudo-random** data. The `TRNG_CTRL_SIM_MODE` flag of the control register is set if simulation
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mode is active.
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**Register Map**
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.TRNG register map (`struct NEORV32_TRNG`)
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[cols="<2,<1,<4,^1,<7"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.5+<| `0xfffa0000` .5+<| `CTRL` <|`0` `TRNG_CTRL_EN` ^| r/w <| TRNG enable
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<|`1` `TRNG_CTRL_FIFO_CLR` ^| -/w <| flush random data FIFO when set; flag auto-clears
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<|`5:2` `TRNG_CTRL_FIFO_MSB : TRNG_CTRL_FIFO_LSB` ^| r/- <| FIFO depth, log2(`IO_TRNG_FIFO`)
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<|`6` `TRNG_CTRL_SIM_MODE` ^| r/- <| simulation mode (PRNG!)
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<|`7` `TRNG_CTRL_AVAIL` ^| r/- <| random data available when set
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.2+<| `0xfffa0004` .2+<| `DATA` <|`7:0` `TRNG_DATA_MSB : TRNG_DATA_LSB` ^| r/- <| random data byte
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<|`31:8` _reserved_ ^| r/- <| reserved, read as zero
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|=======================
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