| .. | ||
| .gitignore | ||
| neorv32_litex_core_complex.vhd | ||
| neorv32_vivado_ip.tcl | ||
| neorv32_vivado_ip.vhd | ||
| README.md | ||
| xbus2ahblite_bridge.vhd | ||
| xbus2axi4lite_bridge.vhd | ||
Processor System Integration
> neorv32_litex_core_complex.vhd
Pre-configured top entity wrapper for integration within the LiteX SoC builder framework. This wrapper provides AXI4-Lite- and AXI4-Stream-compatible interfaces.
Tip
See the user guide section
core/memfor more information.
Note
The provided top entity wrapper can also be used for custom (AXI) setups outside of Vivado IP block designs.
> neorv32_vivado_ip.vhd
Processor top entity with optional AXI4-Lite and AXI4-Stream interfaces. Dedicated for integration as custom IP block within AMD Vivado. Run the provided packaging script in the Vivado TCL shell to generate a NEORV32 IP block:
source neorv32_vivado_ip.tcl
Tip
See the user guide's UG: Packaging the Processor as Vivado IP Block section for more information and step-by-step instructions for generating a NEORV32 IP module.
> xbus2ahblite_bridge.vhd
A simple bridge module that converts the processor's XBUS interface into an AHB3-lite-compatible host interface.