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593 lines
26 KiB
C
593 lines
26 KiB
C
// #################################################################################################
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// # << NEORV32: neorv32_rte.c - NEORV32 Runtime Environment >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_rte.c
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* @author Stephan Nolting
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* @brief NEORV32 Runtime Environment.
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_rte.h"
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/**********************************************************************//**
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* The >private< trap vector look-up table of the NEORV32 RTE.
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**************************************************************************/
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static uint32_t __neorv32_rte_vector_lut[16] __attribute__((unused)); // trap handler vector table
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// private functions
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_hex_word(uint32_t num);
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/**********************************************************************//**
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* Setup NEORV32 runtime environment.
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*
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* @note This function installs a debug handler for ALL exception and interrupt sources, which
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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void neorv32_rte_setup(void) {
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// check if CSR system is available at all
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if (neorv32_cpu_csr_read(CSR_MISA) == 0) {
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neorv32_uart_print("<RTE> WARNING! CPU CSR system not available! </RTE>");
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}
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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// install debug handler for all sources
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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neorv32_rte_exception_uninstall(id); // this will configure the debug handler
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}
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}
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/**********************************************************************//**
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* Install exception handler function to NEORV32 runtime environment.
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*
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* @note Interrupt sources have to be explicitly enabled by the user via the CSR.mie bits via neorv32_cpu_irq_enable(uint8_t irq_sel)
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* and the global interrupt enable bit mstatus.mie via neorv32_cpu_eint(void).
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
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* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
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(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
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(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
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(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* Uninstall exception handler function from NEORV32 runtime environment, which was
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* previously installed via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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*
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* @note Interrupt sources have to be explicitly disabled by the user via the CSR.mie bits via neorv32_cpu_irq_disable(uint8_t irq_sel)
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* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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int neorv32_rte_exception_uninstall(uint8_t id) {
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
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(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
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(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
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(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* This is the core of the NEORV32 RTE.
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*
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* @note This function must no be explicitly used by the user.
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* @note The RTE core uses mscratch CSR to store the trap-causing mepc for further (user-defined) processing.
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*
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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**************************************************************************/
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static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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// compute return address
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if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
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// get low half word of faulting instruction
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register uint32_t rte_trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
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if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction
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rte_mepc += 4;
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}
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else { // faulting instruction is compressed instruction
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rte_mepc += 2;
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}
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// store new return address
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neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
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}
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// find according trap handler
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register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler);
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switch (rte_mcause) {
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case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_L_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
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case TRAP_CODE_L_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_S_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
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case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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default: break;
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}
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// execute handler
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void (*handler_pnt)(void);
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handler_pnt = (void*)rte_handler;
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(*handler_pnt)();
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
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* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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**************************************************************************/
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static void __neorv32_rte_debug_exc_handler(void) {
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// intro
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neorv32_uart_print("<RTE> ");
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// cause
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_print("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_print("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_print("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_print("Breakpoint"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_print("Load address misaligned"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_print("Load access fault"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_print("Store address misaligned"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_print("Store access fault"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_print("Environment call"); break;
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case TRAP_CODE_MSI: neorv32_uart_print("Machine software interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_print("Machine timer interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_print("Machine external interrupt"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_print("Fast interrupt 0"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_print("Fast interrupt 1"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_print("Fast interrupt 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_print("Fast interrupt 3"); break;
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default: neorv32_uart_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
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}
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// instruction address
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neorv32_uart_print(" @ PC=");
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__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores actual mepc to mscratch
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// additional info
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neorv32_uart_print(", MTVAL=");
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__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
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neorv32_uart_print(" </RTE>");
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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**************************************************************************/
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void neorv32_rte_print_hw_config(void) {
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uint32_t tmp;
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int i;
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char c;
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neorv32_uart_printf("\n\n<< Hardware Configuration Overview >>\n");
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// CPU configuration
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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// ID
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neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
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neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
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tmp = neorv32_cpu_csr_read(CSR_MARCHID);
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neorv32_uart_printf("Architecture ID: 0x%x", tmp);
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if (tmp == NEORV32_ARCHID) {
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neorv32_uart_printf(" (NEORV32)");
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}
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// HW version
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neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
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neorv32_rte_print_hw_version();
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neorv32_uart_printf(")\n");
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// CPU architecture
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neorv32_uart_printf("Architecture: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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tmp = (tmp >> 30) & 0x03;
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if (tmp == 0) {
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neorv32_uart_printf("unknown");
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}
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if (tmp == 1) {
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neorv32_uart_printf("RV32");
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}
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if (tmp == 2) {
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neorv32_uart_printf("RV64");
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}
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if (tmp == 3) {
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neorv32_uart_printf("RV128");
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}
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// CPU extensions
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neorv32_uart_printf("\nExtensions: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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for (i=0; i<26; i++) {
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if (tmp & (1 << i)) {
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c = (char)('A' + i);
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neorv32_uart_putc(c);
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neorv32_uart_putc(' ');
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}
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}
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// Z* CPU extensions (from custom CSR "mzext")
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tmp = neorv32_cpu_csr_read(CSR_MZEXT);
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if (tmp & (1<<CPU_MZEXT_ZICSR)) {
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neorv32_uart_printf("Zicsr ");
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}
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if (tmp & (1<<CPU_MZEXT_ZIFENCEI)) {
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neorv32_uart_printf("Zifencei ");
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}
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if (tmp & (1<<CPU_MZEXT_PMP)) {
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neorv32_uart_printf("PMP ");
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}
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// check physical memory protection
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neorv32_uart_printf("\n\nPhysical memory protection: ");
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if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) {
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// check granulartiy
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
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uint32_t pmp_test_g = neorv32_cpu_csr_read(0x3b0);
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// find least-significat set bit
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for (i=31; i!=0; i--) {
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if (((pmp_test_g >> i) & 1) == 0) {
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break;
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}
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}
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neorv32_uart_printf("\n- Min granularity: ");
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if (i < 29) {
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neorv32_uart_printf("%u bytes per region\n", (uint32_t)(1 << (i+1+2)));
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}
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else {
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neorv32_uart_printf("2^%u bytes per region\n", i+1+2);
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}
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// test available modes
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neorv32_uart_printf("- Mode TOR: ");
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0x08);
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if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x08) {
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neorv32_uart_printf("available\n");
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}
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else {
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neorv32_uart_printf("not implemented\n");
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}
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neorv32_uart_printf("- Mode NA4: ");
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0x10);
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if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x10) {
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neorv32_uart_printf("available\n");
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}
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else {
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neorv32_uart_printf("not implemented\n");
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}
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neorv32_uart_printf("- Mode NAPOT: ");
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0x18);
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if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x18) {
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neorv32_uart_printf("available\n");
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}
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else {
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neorv32_uart_printf("not implemented\n");
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}
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// deactivate entry
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0);
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}
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else {
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neorv32_uart_printf("not implemented\n");
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}
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// Misc - system
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neorv32_uart_printf("\n\n-- Processor --\n");
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neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
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neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
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// Memory configuration
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neorv32_uart_printf("\n-- Processor Memory Configuration --\n");
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neorv32_uart_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE);
|
|
neorv32_uart_printf("Internal IMEM: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
|
|
neorv32_uart_printf("IMEM size: %u bytes\n", SYSINFO_IMEM_SIZE);
|
|
neorv32_uart_printf("Internal IMEM as ROM: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
|
|
|
|
neorv32_uart_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
|
|
neorv32_uart_printf("Internal DMEM: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
|
|
neorv32_uart_printf("DMEM size: %u bytes\n", SYSINFO_DMEM_SIZE);
|
|
|
|
neorv32_uart_printf("Bootloader: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
|
|
|
|
neorv32_uart_printf("External M interface: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
|
|
|
|
// peripherals
|
|
neorv32_uart_printf("\n-- Available Processor Peripherals --\n");
|
|
|
|
tmp = SYSINFO_FEATURES;
|
|
|
|
neorv32_uart_printf("GPIO - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
|
|
|
|
neorv32_uart_printf("MTIME - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
|
|
|
|
neorv32_uart_printf("UART - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
|
|
|
|
neorv32_uart_printf("SPI - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
|
|
|
|
neorv32_uart_printf("TWI - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
|
|
|
|
neorv32_uart_printf("PWM - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
|
|
|
|
neorv32_uart_printf("WDT - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
|
|
|
neorv32_uart_printf("TRNG - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
|
|
|
neorv32_uart_printf("CFU0 - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU0));
|
|
|
|
neorv32_uart_printf("CFU1 - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU1));
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print true or false.
|
|
* @note This function is used by neorv32_rte_print_hw_config(void) only.
|
|
*
|
|
* @param[in] state Print TRUE when !=0, print FALSE when 0
|
|
**************************************************************************/
|
|
static void __neorv32_rte_print_true_false(int state) {
|
|
|
|
if (state) {
|
|
neorv32_uart_print("True\n");
|
|
}
|
|
else {
|
|
neorv32_uart_print("False\n");
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print 32-bit number
|
|
* as 8-digit hexadecimal value (with "0x" suffix).
|
|
*
|
|
* @param[in] num Number to print as hexadecimal.
|
|
**************************************************************************/
|
|
void __neorv32_rte_print_hex_word(uint32_t num) {
|
|
|
|
static const char hex_symbols[16] = "0123456789ABCDEF";
|
|
|
|
neorv32_uart_print("0x");
|
|
|
|
int i;
|
|
for (i=0; i<8; i++) {
|
|
uint32_t index = (num >> (28 - 4*i)) & 0xF;
|
|
neorv32_uart_putc(hex_symbols[index]);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Function to show the processor version in human-readable format.
|
|
**************************************************************************/
|
|
void neorv32_rte_print_hw_version(void) {
|
|
|
|
uint32_t i;
|
|
char tmp, cnt;
|
|
|
|
for (i=0; i<4; i++) {
|
|
|
|
tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
|
|
|
|
// serial division
|
|
cnt = 0;
|
|
while (tmp >= 16) {
|
|
tmp = tmp - 16;
|
|
cnt++;
|
|
}
|
|
|
|
if (cnt) {
|
|
neorv32_uart_putc('0' + cnt);
|
|
}
|
|
neorv32_uart_putc('0' + tmp);
|
|
if (i < 3) {
|
|
neorv32_uart_putc('.');
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project credits
|
|
**************************************************************************/
|
|
void neorv32_rte_print_credits(void) {
|
|
|
|
neorv32_uart_print("The NEORV32 Processor Project by Stephan Nolting\n"
|
|
"https://github.com/stnolting/neorv32\n\n");
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project credits
|
|
**************************************************************************/
|
|
void neorv32_rte_print_logo(void) {
|
|
|
|
const uint32_t logo_data_c[11][4] =
|
|
{
|
|
{0b00000000000000000000000000000000,0b00000000000000000000000000000000,0b00000000000000000000000110000000,0b00000000000000000000000000000000},
|
|
{0b00000000000000000000000000000000,0b00000000000000000000000000000000,0b00000000000000000000000110000000,0b00110001100011000000000000000000},
|
|
{0b01100000110001111111110001111111,0b10000111111110001100000011000111,0b11111000011111111000000110000000,0b11111111111111110000000000000000},
|
|
{0b11110000110011000000000011000000,0b11001100000011001100000011001100,0b00001100110000001100000110000011,0b11000000000000111100000000000000},
|
|
{0b11011000110011000000000011000000,0b11001100000011001100000011000000,0b00001100000000011000000110000000,0b11000111111000110000000000000000},
|
|
{0b11001100110011111111100011000000,0b11001111111110001100000011000000,0b11111000000001100000000110000011,0b11000111111000111100000000000000},
|
|
{0b11000110110011000000000011000000,0b11001100001100000110000110000000,0b00001100000110000000000110000000,0b11000111111000110000000000000000},
|
|
{0b11000011110011000000000011000000,0b11001100000110000011001100001100,0b00001100011000000000000110000011,0b11000000000000111100000000000000},
|
|
{0b11000001100001111111110001111111,0b10001100000011000000110000000111,0b11111000111111111100000110000000,0b11111111111111110000000000000000},
|
|
{0b00000000000000000000000000000000,0b00000000000000000000000000000000,0b00000000000000000000000110000000,0b00110001100011000000000000000000},
|
|
{0b00000000000000000000000000000000,0b00000000000000000000000000000000,0b00000000000000000000000110000000,0b00000000000000000000000000000000}
|
|
};
|
|
|
|
int u,v,w;
|
|
uint32_t tmp;
|
|
|
|
for (u=0; u<11; u++) {
|
|
neorv32_uart_print("\n");
|
|
for (v=0; v<4; v++) {
|
|
tmp = logo_data_c[u][v];
|
|
for (w=0; w<32; w++){
|
|
if (tmp & (1 << (31-w))) {
|
|
neorv32_uart_putc('#');
|
|
}
|
|
else {
|
|
neorv32_uart_putc(' ');
|
|
}
|
|
}
|
|
}
|
|
}
|
|
neorv32_uart_print("\n");
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project license
|
|
**************************************************************************/
|
|
void neorv32_rte_print_license(void) {
|
|
|
|
neorv32_uart_print(
|
|
"\n"
|
|
"BSD 3-Clause License\n"
|
|
"\n"
|
|
"Copyright (c) 2020, Stephan Nolting. All rights reserved.\n"
|
|
"\n"
|
|
"Redistribution and use in source and binary forms, with or without modification, are\n"
|
|
"permitted provided that the following conditions are met:\n"
|
|
"\n"
|
|
"1. Redistributions of source code must retain the above copyright notice, this list of\n"
|
|
" conditions and the following disclaimer.\n"
|
|
"\n"
|
|
"2. Redistributions in binary form must reproduce the above copyright notice, this list of\n"
|
|
" conditions and the following disclaimer in the documentation and/or other materials\n"
|
|
" provided with the distribution.\n"
|
|
"\n"
|
|
"3. Neither the name of the copyright holder nor the names of its contributors may be used to\n"
|
|
" endorse or promote products derived from this software without specific prior written\n"
|
|
" permission.\n"
|
|
"\n"
|
|
"THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS\n"
|
|
"OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n"
|
|
"MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n"
|
|
"COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n"
|
|
"EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n"
|
|
"GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n"
|
|
"AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n"
|
|
"NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n"
|
|
"OF THE POSSIBILITY OF SUCH DAMAGE.\n"
|
|
"\n"
|
|
"\n"
|
|
);
|
|
}
|
|
|