mirror of
https://github.com/stnolting/neorv32.git
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312 lines
11 KiB
C
312 lines
11 KiB
C
// ================================================================================ //
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// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
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// Copyright (c) NEORV32 contributors. //
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// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
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// Licensed under the BSD-3-Clause license, see LICENSE for details. //
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// SPDX-License-Identifier: BSD-3-Clause //
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// ================================================================================ //
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/**
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* @file neorv32_cpu.h
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* @brief CPU Core Functions HW driver header file.
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*/
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#ifndef NEORV32_CPU_H
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#define NEORV32_CPU_H
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#include <stdint.h>
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/**********************************************************************//**
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* @name Prototypes
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**************************************************************************/
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/**@{*/
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uint64_t neorv32_cpu_get_cycle(void);
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void neorv32_cpu_set_mcycle(uint64_t value);
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uint64_t neorv32_cpu_get_instret(void);
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void neorv32_cpu_set_minstret(uint64_t value);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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int neorv32_cpu_pmp_configure_region(int index, uint32_t addr, uint8_t config);
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uint32_t neorv32_cpu_hpm_get_num_counters(void);
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uint32_t neorv32_cpu_hpm_get_size(void);
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/**@}*/
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/**********************************************************************//**
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* Restart CPU core (jump to boot address).
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*
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* @warning This is just a "software reset" that uses the in-code reset/boot/entry address linked at compile time.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_soft_restart(void) {
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uint32_t sw_boot_addr = NEORV32_CRT0_ENTRY; // linker symbol
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asm volatile ("jalr x0, 0(%[dst])" : : [dst] "r" (sw_boot_addr));
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__builtin_unreachable();
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while(1); // should never be reached
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}
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/**********************************************************************//**
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* Store unsigned word to address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data word (32-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata) {
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uint32_t reg_addr = addr;
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uint32_t reg_data = wdata;
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asm volatile ("sw %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Store unsigned half-word to address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data half-word (16-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_half(uint32_t addr, uint16_t wdata) {
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uint32_t reg_addr = addr;
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uint32_t reg_data = (uint32_t)wdata;
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asm volatile ("sh %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Store unsigned byte to address space.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data byte (8-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_byte(uint32_t addr, uint8_t wdata) {
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uint32_t reg_addr = addr;
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uint32_t reg_data = (uint32_t)wdata;
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asm volatile ("sb %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Load unsigned word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data word (32-bit).
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_word(uint32_t addr) {
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uint32_t reg_addr = addr;
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uint32_t reg_data;
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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/**********************************************************************//**
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* Load unsigned half-word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data half-word (16-bit).
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**************************************************************************/
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inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) {
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uint32_t reg_addr = addr;
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uint16_t reg_data;
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asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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/**********************************************************************//**
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* Load signed half-word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data half-word (16-bit).
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**************************************************************************/
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inline int16_t __attribute__ ((always_inline)) neorv32_cpu_load_signed_half(uint32_t addr) {
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uint32_t reg_addr = addr;
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int16_t reg_data;
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asm volatile ("lh %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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/**********************************************************************//**
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* Load unsigned byte from address space.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data byte (8-bit).
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**************************************************************************/
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inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) {
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uint32_t reg_addr = addr;
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uint8_t reg_data;
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asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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/**********************************************************************//**
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* Load signed byte from address space.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data byte (8-bit).
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**************************************************************************/
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inline int8_t __attribute__ ((always_inline)) neorv32_cpu_load_signed_byte(uint32_t addr) {
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uint32_t reg_addr = addr;
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int8_t reg_data;
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asm volatile ("lb %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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/**********************************************************************//**
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* Read data from CPU control and status register (CSR).
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*
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* @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum.
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* @return Read data (uint32_t).
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
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uint32_t csr_data;
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asm volatile ("csrr %[dst], %[id]" : [dst] "=r" (csr_data) : [id] "i" (csr_id));
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return csr_data;
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}
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/**********************************************************************//**
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* Write data to CPU control and status register (CSR).
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*
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* @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum.
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* @param[in] data Data to write (uint32_t).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
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uint32_t csr_data = data;
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asm volatile ("csrw %[id], %[src]" : : [id] "i" (csr_id), [src] "r" (csr_data));
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}
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/**********************************************************************//**
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* Set bit(s) in CPU control and status register (CSR).
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*
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* @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum.
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* @param[in] mask Bit mask (high-active) to set bits (uint32_t).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_set(const int csr_id, uint32_t mask) {
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uint32_t csr_data = mask;
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asm volatile ("csrs %[id], %[src]" : : [id] "i" (csr_id), [src] "r" (csr_data));
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}
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/**********************************************************************//**
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* Clear bit(s) in CPU control and status register (CSR).
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*
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* @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum.
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* @param[in] mask Bit mask (high-active) to clear bits (uint32_t).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_clr(const int csr_id, uint32_t mask) {
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uint32_t csr_data = mask;
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asm volatile ("csrc %[id], %[src]" : : [id] "i" (csr_id), [src] "r" (csr_data));
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}
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/**********************************************************************//**
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* Atomic write-after-read CSR operation.
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*
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* @param[in] csr_id ID of CSR. See #NEORV32_CSR_enum.
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* @param[in] wdata New data to write to selected CSR.
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* @return Old data read from selected CSR.
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_swap(const int csr_id, uint32_t wdata) {
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uint32_t tmp;
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asm volatile ("csrrw %[dst], %[id], %[src]" : [dst] "=r" (tmp) : [id] "i" (csr_id), [src] "r" (wdata));
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return tmp;
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}
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/**********************************************************************//**
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* Put CPU into sleep / power-down mode.
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*
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* @note The WFI (wait for interrupt) instruction will make the CPU halt until
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* any enabled interrupt source becomes pending.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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asm volatile ("wfi");
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}
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/**********************************************************************//**
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* Atomic memory access: load-reservate word.
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*
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* @note The address has to be word-aligned - otherwise an alignment exception will be raised.
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* @warning This function requires the A/Zalrsc ISA extension.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data word (32-bit).
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_amolr(uint32_t addr) {
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#if defined __riscv_atomic
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uint32_t amo_addr = addr;
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uint32_t amo_rdata;
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asm volatile ("lr.w %[dst], 0(%[addr])" : [dst] "=r" (amo_rdata) : [addr] "r" (amo_addr));
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return amo_rdata;
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#else
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(void)addr;
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return 0;
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#endif
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}
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/**********************************************************************//**
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* Atomic memory access: store-conditional word.
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*
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* @note The address has to be word-aligned - otherwise an alignment exception will be raised.
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* @warning This function requires the A/Zalrsc ISA extension.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data word to-be-written conditionally (32-bit).
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* @return Status: 0 = ok, 1 = failed (32-bit).
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_amosc(uint32_t addr, uint32_t wdata) {
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#if defined __riscv_atomic
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uint32_t amo_addr = addr;
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uint32_t amo_wdata = wdata;
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uint32_t amo_status;
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asm volatile ("sc.w %[dst], %[src], (%[addr])" : [dst] "=r" (amo_status) : [src] "r" (amo_wdata), [addr] "r" (amo_addr));
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return amo_status;
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#else
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(void)addr;
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(void)wdata;
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return 1; // always fail
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#endif
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}
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#endif // NEORV32_CPU_H
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