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Cleanup

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This commit is contained in:
Olof Kindgren 2018-11-21 13:22:55 +01:00
parent 9df2a0060b
commit 079d973969
11 changed files with 1 additions and 18814 deletions
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70
bench/serv_alu_tb.v
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@ -1,70 +0,0 @@
`default_nettype none
module serv_alu_tb;
reg clk = 1'b1;
reg go;
reg instr;
reg jal;
wire [31:0] pc_data;
wire pc_valid;
reg pc_ready = 1'b1;
wire rd;
wire rd_valid;
wire done;
reg reg11;
reg [8:0] reg2012;
wire reg2012_en;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_ctrl dut
(
.clk (clk),
.i_go (go),
.i_instr (instr),
.i_jal (jal),
.i_reg11 (reg11),
.i_reg2012 (reg2012[0]),
.o_reg2012_en (reg2012_en),
.o_rd (rd),
.o_rd_valid (rd_valid),
.o_pc_data (pc_data),
.o_pc_valid (pc_valid),
.i_pc_ready (pc_ready));
reg [31:0] instruction;
integer idx;
initial begin
instruction = 32'h3d80006f;
reg11 = instruction[20];
reg2012 = {instruction[31],instruction[19:12]};
for (idx=0;idx < 31;idx=idx+1) begin
go <= (idx == 19); //Check this
instr <= instruction[idx];
jal <= (idx > 7);
if (reg2012_en) reg2012 <= (reg2012 >> 1);
@(posedge clk);
end
while (!done)
@(posedge clk);
end // initial begin
reg [31:0] rd_word;
always @(posedge clk) begin
if (rd_valid)
rd_word = {rd, rd_word[31:1]};
if (pc_valid & pc_ready) begin
$display("New PC is %08x", pc_data);
$display("RD is %08x", rd_word);
end
end
endmodule

86
bench/serv_ctrl_tb.v
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@ -1,86 +0,0 @@
`default_nettype none
module serv_ctrl_tb;
reg clk = 1'b1;
reg go;
wire en;
wire jump;
wire [31:0] pc_data;
wire pc_valid;
reg pc_ready = 1'b1;
wire rd;
wire rd_valid;
wire done;
reg reg11;
reg [8:0] reg2012;
wire reg2012_en;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_decode decode
(
.clk (clk),
.i_go (go),
.i_instr (instruction),
.o_ctrl_jump (jump),
.o_ctrl_en (en),
.o_imm (offset),
.o_rd_from_ctrl ());
serv_ctrl
#(.RESET_PC (32'h464))
dut
(
.clk (clk),
.i_en (en),
.i_jump (jump),
.i_offset (offset),
.o_rd (rd),
.o_i_dat (pc_data),
.o_pc_valid (pc_valid),
.i_pc_ready (pc_ready));
reg [31:0] instruction;
integer idx;
reg [20:0] offset;
initial begin
instruction = 32'h3d80006f;
//instruction = 32'h0080706f;
offset = {instruction[31],
instruction[19:12],
instruction[20],
instruction[30:21],1'b0};
$display("Reconstructured offset %08x", offset);
en <= 1'b1;
for (idx=0;idx < 31;idx=idx+1) begin
go <= (idx == 20); //Check this
instr <= instruction[idx];
jal <= (idx > 7);
if (reg2012_en) reg2012 <= (reg2012 >> 1);
@(posedge clk);
end
while (!done)
@(posedge clk);
end // initial begin
reg [31:0] rd_word;
always @(posedge clk) begin
if (rd_valid)
rd_word = {rd, rd_word[31:1]};
if (pc_valid & pc_ready) begin
$display("New PC is %08x", pc_data);
$display("RD is %08x", rd_word);
end
end
endmodule

55
bench/serv_decode_tb.v
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@ -1,55 +0,0 @@
`default_nettype none
module serv_decode_tb;
reg clk = 1'b1;
reg [31:0] i_rd_dat = 32'd0;
reg i_rd_vld = 1'b0;
wire i_rd_rdy;
wire ctrl_en;
wire ctrl_jump;
wire [4:0] rd_addr;
wire [4:0] rs1_addr;
wire [4:0] rs2_addr;
wire imm;
wire offset_source;
wire [1:0] rd_source;
reg [31:0] tb_imm;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_decode decode
(
.clk (clk),
.i_i_rd_dat (i_rd_dat),
.i_i_rd_vld (i_rd_vld),
.o_i_rd_rdy (i_rd_rdy),
.o_ctrl_en (ctrl_en),
.o_ctrl_jump (ctrl_jump),
.o_rf_rd_addr (rd_addr),
.o_rf_rs1_addr (rs1_addr),
.o_rf_rs2_addr (rs2_addr),
.o_imm (imm),
.o_offset_source (offset_source),
.o_rd_source (rd_source));
initial begin
@(posedge clk);
i_rd_dat <= 32'h3d80006f;
i_rd_vld <= 1'b1;
@(posedge clk);
@(posedge i_rd_rdy);
@(posedge clk);
$display("imm = %08x", tb_imm);
$finish;
end
always @(posedge clk) begin
if (ctrl_en)
tb_imm <= {imm, tb_imm[31:1]};
end
endmodule

0
data/dummy.pcf
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16384
firmware.hex
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File diff suppressed because it is too large Load diff

2048
hellomin.hex
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File diff suppressed because it is too large Load diff

55
rtl/camd_ram.v
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@ -1,55 +0,0 @@
module camd_ram
#(//camd parameters
parameter AW = 32,
parameter DW = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input clk_i,
input rst_i,
input [AW-1:0] ca_adr_i, //FIXME width = AW-clog2(WB_DW/8)
input ca_cmd_i,
input ca_vld_i,
output ca_rdy_o,
input [DW-1:0] dm_dat_i,
input [DW/8-1:0] dm_msk_i,
input dm_vld_i,
output dm_rdy_o,
output [DW-1:0] rd_dat_o,
output reg rd_vld_o,
input rd_rdy_i);
wire ca_en = ca_vld_i & ca_rdy_o;
wire dm_en = dm_vld_i & dm_rdy_o;
wire ram_we = ca_en & dm_en;
assign ca_rdy_o = 1'b1;
assign dm_rdy_o = 1'b1;
wire [aw-1:2] raddr;
reg [aw-1:2] latched_raddr;
assign raddr = ca_en ? ca_adr_i[aw-1:2] : latched_raddr;
always @(posedge clk_i) begin
if (ca_en)
latched_raddr <= ca_adr_i[aw-1:2];
rd_vld_o <= 1'b0;
if (ca_en & !ca_cmd_i)
rd_vld_o <= 1'b1;
end
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (clk_i),
.we ({4{ram_we}} & dm_msk_i),
.din (dm_dat_i),
.waddr (ca_adr_i[aw-1:2]),
.raddr (raddr),
.dout (rd_dat_o));
endmodule

5
serv.core
View file

@ -27,9 +27,6 @@ filesets:
- helloservice4000.hex : {copyto : helloservice4000.hex}
file_type : user
pcf:
files:
- data/dummy.pcf : {file_type : PCF}
serv_top_tb:
files:
- bench/serv_top_tb.v
@ -67,7 +64,7 @@ targets:
synth:
default_tool : icestorm
filesets : [core, mem_files, wrapper, pcf]
filesets : [core, mem_files, wrapper, tinyfpga_bx]
toplevel : serv_wrapper
tinyfpga_bx:

45
serv_top_tb.v
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@ -1,45 +0,0 @@
module serv_top_tb;
reg clk = 1'b1;
always #5 clk <= !clk;
vlog_tb_utils vtu();
reg [1023:0] firmware_file;
reg [31:0] memory [0:16383];
reg [31:0] i_data;
reg i_valid = 1'b0;
wire i_ready;
wire [31:0] pc_data;
wire pc_valid;
reg pc_ready = 1'b0;
initial begin
firmware_file = "firmware.hex";
$readmemh(firmware_file, memory);
end
always @(posedge clk) begin
pc_ready <= 1'b1; //Fuck knows
if (i_valid & i_ready)
i_valid <= 1'b0;
if (pc_valid & pc_ready) begin
i_data <= memory[pc_data>>2];
i_valid <= 1'b1;
pc_ready <= 1'b0;
end
end
serv_top dut
(.clk (clk),
.i_i_data (i_data),
.i_i_valid (i_valid),
.o_i_ready (i_ready),
.o_pc_data (pc_data),
.o_pc_valid (pc_valid),
.i_pc_ready (pc_ready));
endmodule

21
testhalt.v
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@ -1,21 +0,0 @@
`default_nettype none
module testhalt
(
input wire i_wb_clk,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg o_wb_ack = 1'b0);
always @(posedge i_wb_clk) begin
`ifndef SYNTHESIS
if (i_wb_cyc & i_wb_stb) begin
$display("Test complete");
$finish;
end
`endif
if (i_wb_cyc & i_wb_stb & !o_wb_ack)
o_wb_ack <= 1'b1;
end
endmodule

46
testprint.v
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@ -1,46 +0,0 @@
`default_nettype none
module testprint
(
input wire i_wb_clk,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg o_wb_ack = 1'b0);
wire wb_en;
wire [7:0] ch;
assign ch = i_wb_dat[7:0];
assign wb_en = i_wb_cyc & i_wb_stb;
`ifndef SYNTHESIS
//synthesis translate_off
reg [1023:0] signature_file;
integer f = 0;
initial
if ($value$plusargs("signature=%s", signature_file)) begin
$display("Writing signature to %0s", signature_file);
f = $fopen(signature_file, "w");
end
//synthesis translate_on
`endif
always @(posedge i_wb_clk) begin
o_wb_ack <= 1'b0;
`ifndef SYNTHESIS
//synthesis translate_off
if (wb_en & o_wb_ack) begin
if (f)
$fwrite(f, "%c", i_wb_dat[7:0]);
$write("%c", i_wb_dat[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
//synthesis translate_on
`endif
if (wb_en & !o_wb_ack)
o_wb_ack <= 1'b1;
end
endmodule