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https://github.com/olofk/serv.git
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Make counter internal in serv_state
This commit is contained in:
Olof Kindgren
parent
3829d05786
commit
1d311edb7d
6 changed files with 73 additions and 36 deletions
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@ -4,6 +4,7 @@ module serv_alu
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input wire clk,
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input wire i_rst,
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input wire i_en,
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input wire i_cnt0,
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input wire i_rs1,
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input wire i_rs2,
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input wire i_imm,
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@ -33,7 +34,6 @@ module serv_alu
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wire [4:0] shamt;
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reg shamt_msb;
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reg en_r;
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wire shamt_ser;
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wire plus_1;
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@ -82,7 +82,7 @@ module serv_alu
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assign result_eq = eq & eq_r;
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assign result_lt = eq ? lt_r : op_b^lt_sign;
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assign plus_1 = i_en & !en_r;
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assign plus_1 = i_cnt0;
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assign o_cmp = i_cmp_eq ? result_eq : result_lt;
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localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
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@ -104,7 +104,6 @@ module serv_alu
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result_lt_r <= result_lt;
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end
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eq_r <= result_eq | ~i_en;
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en_r <= i_en;
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if (i_shamt_en)
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shamt_msb <= b_inv_plus_1_cy;
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@ -1,8 +1,8 @@
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module serv_bufreg
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(
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input wire i_clk,
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input wire [4:2] i_cnt,
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input wire [1:0] i_cnt_r,
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input wire i_cnt0,
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input wire i_cnt1,
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input wire i_en,
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input wire i_init,
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input wire i_loop,
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@ -19,7 +19,7 @@ module serv_bufreg
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reg c_r;
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reg [31:0] data;
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wire clr_lsb = (i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_clr_lsb;
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wire clr_lsb = i_cnt0 & i_clr_lsb;
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assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r;
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@ -30,9 +30,9 @@ module serv_bufreg
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if (i_en)
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data <= {(i_loop & !i_init) ? o_q : q, data[31:1]};
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if ((i_cnt[4:2] == 3'd0) & i_cnt_r[0] & i_init)
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if (i_cnt0 & i_init)
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o_lsb[0] <= q;
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if ((i_cnt[4:2] == 3'd0) & i_cnt_r[1] & i_init)
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if (i_cnt1 & i_init)
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o_lsb[1] <= q;
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end
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@ -3,8 +3,11 @@ module serv_csr
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(
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input wire i_clk,
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input wire i_en,
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input wire [4:2] i_cnt,
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input wire [3:2] i_cnt_r,
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input wire i_cnt0to3,
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input wire i_cnt2,
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input wire i_cnt3,
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input wire i_cnt7,
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input wire i_cnt_done,
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input wire i_e_op,
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input wire i_ebreak,
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input wire i_mem_cmd,
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@ -56,8 +59,8 @@ module serv_csr
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wire timer_irq = i_mtip & mstatus_mie & mie_mtie;
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assign mcause = (i_cnt[4:2] == 3'd0) ? mcause3_0[0] : //[3:0]
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((i_cnt[4:2] == 3'd7) & i_cnt_r[3]) ? mcause31 //[31]
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assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0]
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i_cnt_done ? mcause31 //[31]
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: 1'b0;
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assign o_csr_in = csr_in;
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@ -70,13 +73,13 @@ module serv_csr
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Note: To save resources mstatus_mpie (mstatus bit 7) is not
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readable or writable from sw
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*/
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if (i_mstatus_en & (i_cnt[4:2] == 3'd0) & i_cnt_r[3])
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if (i_mstatus_en & i_cnt3)
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mstatus_mie <= csr_in;
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if (i_mie_en & (i_cnt[4:2] == 3'd1) & i_cnt_r[3])
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if (i_mie_en & i_cnt7)
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mie_mtie <= csr_in;
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mstatus <= (i_cnt[4:2] == 0) & i_cnt_r[2] & mstatus_mie;
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mstatus <= i_cnt2 & mstatus_mie;
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timer_irq_r <= timer_irq;
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@ -95,9 +98,9 @@ module serv_csr
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end
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if (i_mcause_en & i_en) begin
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if (i_cnt[4:2] == 3'd0)
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if (i_cnt0to3)
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mcause3_0 <= {csr_in, mcause3_0[3:1]};
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if ((i_cnt[4:2] == 3'd7) & i_cnt_r[3])
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if (i_cnt_done)
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mcause31 <= csr_in;
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end
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end
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@ -5,8 +5,8 @@ module serv_ctrl
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input wire i_rst,
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//State
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input wire i_pc_en,
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input wire [4:2] i_cnt,
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input wire [2:2] i_cnt_r,
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input wire i_cnt12to31,
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input wire i_cnt2,
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input wire i_cnt_done,
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//Control
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input wire i_jump,
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@ -46,7 +46,7 @@ module serv_ctrl
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wire offset_a;
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wire offset_b;
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assign plus_4 = i_cnt_r[2] & (i_cnt[4:2] == 3'd0);
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assign plus_4 = i_cnt2;
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assign o_ibus_adr[0] = pc;
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assign o_bad_pc = pc_plus_offset_aligned;
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@ -76,7 +76,7 @@ module serv_ctrl
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assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);
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assign offset_a = i_pc_rel & pc;
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assign offset_b = i_utype ? (i_imm & (i_cnt[4] | (i_cnt[3:2] == 2'b11))): i_buf;
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assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf;
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assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r;
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assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
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@ -20,8 +20,13 @@ module serv_state
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input wire i_rd_op,
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output reg o_init,
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output reg o_cnt_en,
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output reg [4:0] o_cnt,
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output reg [3:0] o_cnt_r,
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output wire o_cnt0,
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output wire o_cnt0to3,
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output wire o_cnt12to31,
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output wire o_cnt1,
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output wire o_cnt2,
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output wire o_cnt3,
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output wire o_cnt7,
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output wire o_ctrl_pc_en,
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output reg o_ctrl_jump,
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output wire o_ctrl_trap,
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@ -36,15 +41,31 @@ module serv_state
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parameter WITH_CSR = 1;
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wire cnt4;
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reg stage_two_req;
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reg [4:2] o_cnt;
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reg [3:0] o_cnt_r;
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//Update PC in RUN or TRAP states
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assign o_ctrl_pc_en = o_cnt_en & !o_init;
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assign o_alu_shamt_en = (o_cnt < 5) & o_init;
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assign o_mem_bytecnt = o_cnt[4:3];
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assign o_cnt0to3 = (o_cnt[4:2] == 3'd0);
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assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11));
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assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0];
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assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1];
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assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2];
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assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3];
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assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0];
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assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3];
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assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init;
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//slt*, branch/jump, shift, load/store
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wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op;
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@ -90,12 +111,12 @@ module serv_state
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if (o_cnt_done)
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o_cnt_en <= 1'b0;
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o_cnt <= o_cnt + {4'd0,o_cnt_en};
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o_cnt <= o_cnt + {2'd0,o_cnt_r[3]};
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if (o_cnt_en)
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o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]};
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if (i_rst) begin
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o_cnt <= 5'd0;
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o_cnt <= 3'd0;
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stage_two_pending <= 1'b0;
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o_ctrl_jump <= 1'b0;
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o_cnt_r <= 4'b0001;
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@ -88,8 +88,13 @@ module serv_top
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wire init;
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wire cnt_en;
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wire [4:0] cnt;
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wire [3:0] cnt_r;
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wire cnt0to3;
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wire cnt12to31;
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wire cnt0;
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wire cnt1;
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wire cnt2;
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wire cnt3;
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wire cnt7;
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wire cnt_done;
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@ -167,8 +172,13 @@ module serv_top
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.i_rd_op (rd_op),
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.o_init (init),
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.o_cnt_en (cnt_en),
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.o_cnt (cnt),
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.o_cnt_r (cnt_r),
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.o_cnt0to3 (cnt0to3),
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.o_cnt12to31 (cnt12to31),
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.o_cnt0 (cnt0),
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.o_cnt1 (cnt1),
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.o_cnt2 (cnt2),
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.o_cnt3 (cnt3),
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.o_cnt7 (cnt7),
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.o_cnt_done (cnt_done),
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.o_bufreg_hold (bufreg_hold),
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.o_ctrl_pc_en (ctrl_pc_en),
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@ -246,8 +256,8 @@ module serv_top
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serv_bufreg bufreg
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(
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.i_clk (clk),
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.i_cnt (cnt[4:2]),
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.i_cnt_r (cnt_r[1:0]),
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.i_cnt0 (cnt0),
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.i_cnt1 (cnt1),
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.i_en (!bufreg_hold),
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.i_init (init),
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.i_loop (bufreg_loop),
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@ -269,8 +279,8 @@ module serv_top
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.i_rst (i_rst),
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//State
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.i_pc_en (ctrl_pc_en),
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.i_cnt (cnt[4:2]),
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.i_cnt_r (cnt_r[2]),
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.i_cnt12to31 (cnt12to31),
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.i_cnt2 (cnt2),
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.i_cnt_done (cnt_done),
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//Control
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.i_jump (jump),
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@ -295,6 +305,7 @@ module serv_top
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.clk (clk),
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.i_rst (i_rst),
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.i_en (cnt_en),
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.i_cnt0 (cnt0),
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.i_rs1 (rs1),
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.i_rs2 (rs2),
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.i_imm (imm),
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@ -392,8 +403,11 @@ module serv_top
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(
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.i_clk (clk),
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.i_en (cnt_en),
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.i_cnt (cnt[4:2]),
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.i_cnt_r (cnt_r[3:2]),
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.i_cnt0to3 (cnt0to3),
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.i_cnt2 (cnt2),
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.i_cnt3 (cnt3),
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.i_cnt7 (cnt7),
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.i_cnt_done (cnt_done),
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.i_e_op (e_op),
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.i_ebreak (ebreak),
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.i_mem_cmd (o_dbus_we),
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