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Update support for compliance tests version 2.7.4

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This commit is contained in:
Olof Kindgren 2022-06-13 10:47:48 +00:00
parent a8f7de9e8c
commit 2611c89cbe
1 changed files with 24 additions and 12 deletions
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36
.github/workflows/ci.yml vendored
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@ -23,24 +23,36 @@ jobs:
- name: setup workspace
run: fusesoc library add serv $SERV
- name: Add MDU core as a library
run: fusesoc library add mdu https://github.com/zeeshanrafique23/mdu
- name: build servant
run: fusesoc run --target=verilator_tb --build --build-root=servant_x servant
run: fusesoc run --target=verilator_tb --flag=mdu --build --build-root=servant_x servant --memsize=8388608 --compressed=1
- name: download risc-v compliance
run: git clone https://github.com/riscv/riscv-compliance --branch 1.0
- name: download riscv-arch-test version 2.7.4
run: git clone https://github.com/riscv-non-isa/riscv-arch-test.git --branch 2.7.4
- name: run RV32i compliance tests
- name: run RV32 I compliance tests
run: |
cd $GITHUB_WORKSPACE/riscv-compliance
make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
cd $GITHUB_WORKSPACE/riscv-arch-test
make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
- name: run RV32Zicsr compliance tests
- name: run RV32 C compliance tests
run: |
cd $GITHUB_WORKSPACE/riscv-compliance
make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32Zicsr TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
cd $GITHUB_WORKSPACE/riscv-arch-test
make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=C TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
- name: run RV32Zifencei compliance tests
- name: run RV32 M compliance tests
run: |
cd $GITHUB_WORKSPACE/riscv-compliance
make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32Zifencei TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
cd $GITHUB_WORKSPACE/riscv-arch-test
make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=M TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
- name: run RV32 Zifencei compliance tests
run: |
cd $GITHUB_WORKSPACE/riscv-arch-test
make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=Zifencei TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
# - name: run RV32 privilege compliance tests
# run: |
# cd $GITHUB_WORKSPACE/riscv-arch-test
# make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=privilege TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim