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support for W=4

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uhit332 2023-10-31 13:32:29 +01:00 • committed by Olof Kindgren
parent f9d6b23543
commit 46a820ee42
1 changed files with 21 additions and 7 deletions
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28
rtl/serv_state.v
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@ -2,7 +2,9 @@ module serv_state
#(parameter RESET_STRATEGY = "MINI",
parameter [0:0] WITH_CSR = 1,
parameter [0:0] ALIGN =0,
parameter [0:0] MDU = 0)
parameter [0:0] MDU = 0,
parameter W = 1
)
(
input wire i_clk,
input wire i_rst,
@ -174,18 +176,30 @@ module serv_state
just need to check if cnt_r is not zero to see if the counter is
currently running
*/
o_cnt <= o_cnt + {2'd0,cnt_r[3]};
cnt_r <= {cnt_r[2:0],(cnt_r[3] & !o_cnt_done) | (i_rf_ready & !o_cnt_en)};
if (W == 4) begin
if (i_rf_ready) o_cnt_en <= 1; else
if (o_cnt_done) o_cnt_en <= 0;
o_cnt <= o_cnt + { 2'b0, o_cnt_en };
end else if (W == 1) begin
o_cnt <= o_cnt + {2'd0,cnt_r[3]};
cnt_r <= {cnt_r[2:0],(cnt_r[3] & !o_cnt_done) | (i_rf_ready & !o_cnt_en)};
end
if (i_rst) begin
if (RESET_STRATEGY != "NONE") begin
o_cnt <= 3'd0;
cnt_r <= 4'b0000;
end
if (RESET_STRATEGY != "NONE") begin
o_cnt <= 3'd0;
if (W == 1)
cnt_r <= 4'b0000;
else if (W == 4)
o_cnt_en <= 1'b0;
end
end
end
always @(*)
if (W == 1)
o_cnt_en = |cnt_r;
else if (W == 4)
cnt_r = 4'b1111;
assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync);