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Use one-hot encoding for ALU rd sel

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Olof Kindgren 2019-12-07 23:36:36 +01:00
parent eb5d25ea1c
commit 6067b0e684
4 changed files with 11 additions and 25 deletions
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12
rtl/serv_alu.v
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@ -20,11 +20,9 @@ module serv_alu
input wire i_sh_right,
input wire i_sh_signed,
output wire o_sh_done,
input wire [1:0] i_rd_sel,
input wire [3:0] i_rd_sel,
output wire o_rd);
`include "serv_params.vh"
wire result_add;
wire result_eq;
wire result_lt;
@ -106,10 +104,10 @@ module serv_alu
localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}];
assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :
(i_rd_sel == ALU_RESULT_SR) ? result_sh :
(i_rd_sel == ALU_RESULT_LT) ? result_lt_r & plus_1:
(i_rd_sel == ALU_RESULT_BOOL) ? result_bool : 1'bx;
assign o_rd = (i_rd_sel[0] & result_add) |
(i_rd_sel[1] & result_sh) |
(i_rd_sel[2] & result_lt_r & plus_1) |
(i_rd_sel[3] & result_bool);
reg eq_r;

16
rtl/serv_decode.v
View file

@ -33,7 +33,7 @@ module serv_decode
output wire o_alu_cmp_uns,
output wire o_alu_sh_signed,
output wire o_alu_sh_right,
output reg [1:0] o_alu_rd_sel,
output wire [3:0] o_alu_rd_sel,
//To RF
output wire o_rf_rd_en,
output reg [4:0] o_rf_rd_addr,
@ -175,16 +175,10 @@ module serv_decode
reg [4:0] imm24_20;
reg [4:0] imm11_7;
always @(funct3)
casez(funct3)
3'b000 : o_alu_rd_sel = ALU_RESULT_ADD;
3'b001 : o_alu_rd_sel = ALU_RESULT_SR;
3'b01? : o_alu_rd_sel = ALU_RESULT_LT;
3'b100 : o_alu_rd_sel = ALU_RESULT_BOOL;
3'b101 : o_alu_rd_sel = ALU_RESULT_SR;
3'b11? : o_alu_rd_sel = ALU_RESULT_BOOL;
endcase
assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift
assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT*
assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool
always @(posedge clk) begin
if (i_wb_en) begin
o_rf_rd_addr <= i_wb_rdt[11:7];

6
rtl/serv_params.vh
View file

@ -1,9 +1,3 @@
localparam[1:0]
ALU_RESULT_ADD = 2'd0,
ALU_RESULT_SR = 2'd1,
ALU_RESULT_LT = 2'd2,
ALU_RESULT_BOOL = 2'd3;
localparam [1:0]
CSR_SOURCE_CSR = 2'b00,
CSR_SOURCE_EXT = 2'b01,

2
rtl/serv_top.v
View file

@ -106,7 +106,7 @@ module serv_top
wire alu_sh_signed;
wire alu_sh_right;
wire alu_sh_done;
wire [1:0] alu_rd_sel;
wire [3:0] alu_rd_sel;
wire rs1;
wire rs2;