Add upduino2 servant target

data/upduino2.pcf

@@ -0,0 +1,4 @@
+set_io g 39
+set_io b 40
+set_io r 41
+set_io q 14

servant.core

@@ -65,6 +65,11 @@ filesets:
       - servant/servant_ecp5_clock_gen.v : {file_type : verilogSource}
       - servant/servant_ecp5.v : {file_type : verilogSource}
 
+  upduino2:
+    files:
+      - servant/servant_upduino2.v : {file_type : verilogSource}
+      - data/upduino2.pcf : {file_type : PCF}
+
   zcu106:
     files:
       - servant/servus_clock_gen.v : {file_type : verilogSource}
@@ -166,6 +171,16 @@ targets:
         nextpnr_options : [--package, CABGA381, --85k]
     toplevel: servant_ecp5
 
+  upduino2:
+    default_tool : icestorm
+    filesets : [mem_files, soc, upduino2]
+    parameters : [memfile, memsize]
+    tools:
+      icestorm:
+        nextpnr_options: [--package, sg48, --up5k, --freq, 24]
+        pnr: next
+    toplevel : servant_upduino2
+
   verilator_tb:
     default_tool: verilator
     filesets : [soc, servant_tb]

servant/servant_upduino2.v

@@ -0,0 +1,77 @@
+`default_nettype none
+module servant_upduino2
+  (
+   output wire g,
+   output wire b,
+   output wire r,
+   output wire q);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+   parameter PLL = "NONE";
+
+   wire        clk;
+   wire        clk48;
+   wire        locked;
+
+   SB_HFOSC inthosc
+     (
+      .CLKHFPU(1'b1),
+      .CLKHFEN(1'b1),
+      .CLKHF(clk48));
+
+   SB_PLL40_CORE
+     #(
+       .FEEDBACK_PATH("SIMPLE"),
+       .DIVR(4'b0010),
+       .DIVF(7'b0111111),
+       .DIVQ(3'b110),
+       .FILTER_RANGE(3'b001))
+   pll
+     (.LOCK(locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(clk48),
+      .PLLOUTCORE(clk));
+
+   SB_RGBA_DRV
+     #(
+       .CURRENT_MODE ("0b1"),
+       .RGB0_CURRENT ("0b000111"),
+       .RGB1_CURRENT ("0b000111"),
+       .RGB2_CURRENT ("0b000111"))
+   RGBA_DRIVER
+     (
+      .CURREN(1'b1),
+      .RGBLEDEN(1'b1),
+      .RGB0PWM(q),
+      .RGB1PWM(q),
+      .RGB2PWM(q),
+      .RGB0(g),
+      .RGB1(b),
+      .RGB2(r));
+
+   reg 	     rst = 1'b1;
+
+/*
+   //Delayed reset
+   reg [25:0] cnt;
+   always @(posedge clk) begin
+      if (!cnt[25])
+	cnt <= cnt + 1;
+      rst <= !cnt[25];
+   end
+ */
+
+   always @(posedge clk)
+     rst <= !locked;
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (clk),
+      .wb_rst (rst),
+      .q      (q));
+
+endmodule