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46 lines
1.1 KiB
Systemverilog
46 lines
1.1 KiB
Systemverilog
`default_nettype none
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module servant_ram
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#(//Memory parameters
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parameter depth = 256,
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parameter aw = $clog2(depth),
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parameter RESET_STRATEGY = "",
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parameter memfile = "")
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(input wire i_wb_clk,
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input wire i_wb_rst,
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input wire [aw-1:2] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_cyc,
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output reg [31:0] o_wb_rdt,
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output reg o_wb_ack);
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wire we = i_wb_we & i_wb_cyc;
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logic [3:0][7:0] mem[0:depth/4-1];
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wire [aw-3:0] addr = i_wb_adr[aw-1:2];
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always @(posedge i_wb_clk)
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if (i_wb_rst & (RESET_STRATEGY != "NONE"))
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o_wb_ack <= 1'b0;
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else
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o_wb_ack <= i_wb_cyc & !o_wb_ack;
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always_ff @(posedge i_wb_clk) begin
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if(we) begin
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if(i_wb_sel[0]) mem[addr][0] <= i_wb_dat[7:0];
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if(i_wb_sel[1]) mem[addr][1] <= i_wb_dat[15:8];
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if(i_wb_sel[2]) mem[addr][2] <= i_wb_dat[23:16];
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if(i_wb_sel[3]) mem[addr][3] <= i_wb_dat[31:24];
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end
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o_wb_rdt <= mem[addr];
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end
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initial
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if(|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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endmodule
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