mirror of
https://github.com/olofk/serv.git
synced 2025-04-20 11:57:07 -04:00
100 lines
2.3 KiB
Verilog
100 lines
2.3 KiB
Verilog
`default_nettype none
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module serv_ctrl
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(
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input wire clk,
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input wire i_rst,
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//State
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input wire i_pc_en,
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input wire i_cnt12to31,
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input wire i_cnt2,
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input wire i_cnt_done,
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//Control
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input wire i_jump,
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input wire i_jal_or_jalr,
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input wire i_utype,
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input wire i_pc_rel,
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input wire i_trap,
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//Data
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input wire i_imm,
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input wire i_buf,
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input wire i_csr_pc,
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output wire o_rd,
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output wire o_bad_pc,
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//External
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire i_ibus_ack);
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parameter RESET_PC = 32'd0;
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parameter WITH_CSR = 1;
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reg en_pc_r;
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wire pc_plus_4;
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wire pc_plus_4_cy;
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reg pc_plus_4_cy_r;
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wire pc_plus_offset;
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wire pc_plus_offset_cy;
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reg pc_plus_offset_cy_r;
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wire pc_plus_offset_aligned;
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wire plus_4;
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wire pc;
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wire new_pc;
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wire offset_a;
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wire offset_b;
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assign plus_4 = i_cnt2;
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assign o_ibus_adr[0] = pc;
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assign o_bad_pc = pc_plus_offset_aligned;
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assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
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shift_reg
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#(
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.LEN (32),
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.INIT (RESET_PC))
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pc_reg
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_en (i_pc_en),
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.i_d (new_pc),
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.o_q (pc),
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.o_par (o_ibus_adr[31:1])
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);
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generate
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if (WITH_CSR)
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assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
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else
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assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
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endgenerate
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assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);
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assign offset_a = i_pc_rel & pc;
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assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf;
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assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r;
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assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
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assign o_ibus_cyc = en_pc_r & !i_pc_en;
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always @(posedge clk) begin
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pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
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pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
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if (i_pc_en)
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en_pc_r <= 1'b1;
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else if (o_ibus_cyc & i_ibus_ack)
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en_pc_r <= 1'b0;
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if (i_rst) begin
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en_pc_r <= 1'b1;
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end
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end
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endmodule
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