mirror of
https://github.com/olofk/serv.git
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376dcd701d
Expose the width (or W internally) parameter to set the SERV datapath width. Note: Only width=1 is function at this time.
147 lines
4 KiB
Verilog
147 lines
4 KiB
Verilog
/* serving.v : Top-level for the serving SoC
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*
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* ISC License
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*
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* Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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`default_nettype none
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module serving
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_timer_irq,
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output wire [31:0] o_wb_adr,
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output wire [31:0] o_wb_dat,
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output wire [3:0] o_wb_sel,
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output wire o_wb_we ,
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output wire o_wb_stb,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_ack);
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parameter memfile = "";
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parameter memsize = 8192;
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parameter sim = 1'b0;
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parameter RESET_STRATEGY = "NONE";
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parameter WITH_CSR = 1;
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localparam regs = 32+WITH_CSR*4;
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localparam rf_width = 8;
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wire [31:0] wb_mem_adr;
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wire [31:0] wb_mem_dat;
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wire [3:0] wb_mem_sel;
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wire wb_mem_we;
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wire wb_mem_stb;
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wire [31:0] wb_mem_rdt;
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wire wb_mem_ack;
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wire [6+WITH_CSR:0] rf_waddr;
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wire [rf_width-1:0] rf_wdata;
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wire rf_wen;
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wire [6+WITH_CSR:0] rf_raddr;
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wire [rf_width-1:0] rf_rdata;
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wire rf_ren;
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wire [$clog2(memsize)-1:0] sram_waddr;
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wire [rf_width-1:0] sram_wdata;
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wire sram_wen;
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wire [$clog2(memsize)-1:0] sram_raddr;
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wire [rf_width-1:0] sram_rdata;
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wire sram_ren;
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serving_ram
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#(.memfile (memfile),
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.depth (memsize))
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ram
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(// Wishbone interface
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.i_clk (i_clk),
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.i_waddr (sram_waddr),
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.i_wdata (sram_wdata),
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.i_wen (sram_wen),
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.i_raddr (sram_raddr),
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.o_rdata (sram_rdata)/*,
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.i_ren (rf_ren)*/);
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servile_rf_mem_if
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#(.depth (memsize),
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.rf_regs (regs))
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rf_mem_if
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(// Wishbone interface
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_waddr (rf_waddr),
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.i_wdata (rf_wdata),
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.i_wen (rf_wen),
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.i_raddr (rf_raddr),
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.o_rdata (rf_rdata),
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.i_ren (rf_ren),
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.o_sram_waddr (sram_waddr),
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.o_sram_wdata (sram_wdata),
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.o_sram_wen (sram_wen),
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.o_sram_raddr (sram_raddr),
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.i_sram_rdata (sram_rdata),
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.o_sram_ren (sram_ren),
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.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
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.i_wb_stb (wb_mem_stb),
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.i_wb_we (wb_mem_we) ,
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.i_wb_sel (wb_mem_sel),
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.i_wb_dat (wb_mem_dat),
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.o_wb_rdt (wb_mem_rdt),
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.o_wb_ack (wb_mem_ack));
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servile
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#(.reset_pc (32'h0000_0000),
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.reset_strategy (RESET_STRATEGY),
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.rf_width (rf_width),
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.sim (sim),
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.with_csr (WITH_CSR))
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servile
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(
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.i_clk (i_clk),
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.i_rst (i_rst),
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.i_timer_irq (i_timer_irq),
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//Memory interface
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.o_wb_mem_adr (wb_mem_adr),
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.o_wb_mem_dat (wb_mem_dat),
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.o_wb_mem_sel (wb_mem_sel),
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.o_wb_mem_we (wb_mem_we),
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.o_wb_mem_stb (wb_mem_stb),
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.i_wb_mem_rdt (wb_mem_rdt),
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.i_wb_mem_ack (wb_mem_ack),
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//Extension interface
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.o_wb_ext_adr (o_wb_adr),
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.o_wb_ext_dat (o_wb_dat),
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.o_wb_ext_sel (o_wb_sel),
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.o_wb_ext_we (o_wb_we),
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.o_wb_ext_stb (o_wb_stb),
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.i_wb_ext_rdt (i_wb_rdt),
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.i_wb_ext_ack (i_wb_ack),
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//RF IF
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.o_rf_waddr (rf_waddr),
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.o_rf_wdata (rf_wdata),
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.o_rf_wen (rf_wen),
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.o_rf_raddr (rf_raddr),
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.o_rf_ren (rf_ren),
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.i_rf_rdata (rf_rdata));
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endmodule
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