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cd60abe837
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335 lines
11 KiB
Verilog
335 lines
11 KiB
Verilog
module serv_debug
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#(parameter W = 1,
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parameter RESET_PC = 0,
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//Internally calculated. Do not touch
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parameter B=W-1)
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(
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`ifdef RISCV_FORMAL
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output reg rvfi_valid = 1'b0,
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output reg [63:0] rvfi_order = 64'd0,
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output reg [31:0] rvfi_insn = 32'd0,
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output reg rvfi_trap = 1'b0,
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output reg rvfi_halt = 1'b0, // Not used
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output reg rvfi_intr = 1'b0, // Not used
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output reg [1:0] rvfi_mode = 2'b11, // Not used
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output reg [1:0] rvfi_ixl = 2'b01, // Not used
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output reg [4:0] rvfi_rs1_addr,
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output reg [4:0] rvfi_rs2_addr,
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output reg [31:0] rvfi_rs1_rdata,
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output reg [31:0] rvfi_rs2_rdata,
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output reg [4:0] rvfi_rd_addr,
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output wire [31:0] rvfi_rd_wdata,
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output reg [31:0] rvfi_pc_rdata,
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output wire [31:0] rvfi_pc_wdata,
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output reg [31:0] rvfi_mem_addr,
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output reg [3:0] rvfi_mem_rmask,
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output reg [3:0] rvfi_mem_wmask,
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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input wire [31:0] i_dbus_adr,
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input wire [31:0] i_dbus_dat,
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input wire [3:0] i_dbus_sel,
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input wire i_dbus_we,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack,
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input wire i_ctrl_pc_en,
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input wire [B:0] rs1,
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input wire [B:0] rs2,
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input wire [4:0] rs1_addr,
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input wire [4:0] rs2_addr,
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input wire [3:0] immdec_en,
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input wire rd_en,
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input wire trap,
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input wire i_rf_ready,
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input wire i_ibus_cyc,
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input wire two_stage_op,
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input wire init,
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input wire [31:0] i_ibus_adr,
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`endif
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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input wire [4:0] i_rd_addr,
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input wire i_cnt_en,
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input wire [B:0] i_csr_in,
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input wire i_csr_mstatus_en,
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input wire i_csr_mie_en,
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input wire i_csr_mcause_en,
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input wire i_csr_en,
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input wire [1:0] i_csr_addr,
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input wire i_wen0,
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input wire [B:0] i_wdata0,
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input wire i_cnt_done);
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reg update_rd = 1'b0;
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reg [31:0] dbg_rd = 32'hxxxxxxxx;
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reg [31:0] dbg_csr = 32'hxxxxxxxx;
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reg [31:0] dbg_mstatus = 32'hxxxxxxxx;
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reg [31:0] dbg_mie = 32'hxxxxxxxx;
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reg [31:0] dbg_mcause = 32'hxxxxxxxx;
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reg [31:0] dbg_mscratch = 32'hxxxxxxxx;
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reg [31:0] dbg_mtvec = 32'hxxxxxxxx;
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reg [31:0] dbg_mepc = 32'hxxxxxxxx;
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reg [31:0] dbg_mtval = 32'hxxxxxxxx;
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reg [31:0] x1 = 32'hxxxxxxxx;
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reg [31:0] x2 = 32'hxxxxxxxx;
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reg [31:0] x3 = 32'hxxxxxxxx;
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reg [31:0] x4 = 32'hxxxxxxxx;
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reg [31:0] x5 = 32'hxxxxxxxx;
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reg [31:0] x6 = 32'hxxxxxxxx;
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reg [31:0] x7 = 32'hxxxxxxxx;
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reg [31:0] x8 = 32'hxxxxxxxx;
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reg [31:0] x9 = 32'hxxxxxxxx;
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reg [31:0] x10 = 32'hxxxxxxxx;
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reg [31:0] x11 = 32'hxxxxxxxx;
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reg [31:0] x12 = 32'hxxxxxxxx;
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reg [31:0] x13 = 32'hxxxxxxxx;
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reg [31:0] x14 = 32'hxxxxxxxx;
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reg [31:0] x15 = 32'hxxxxxxxx;
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reg [31:0] x16 = 32'hxxxxxxxx;
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reg [31:0] x17 = 32'hxxxxxxxx;
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reg [31:0] x18 = 32'hxxxxxxxx;
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reg [31:0] x19 = 32'hxxxxxxxx;
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reg [31:0] x20 = 32'hxxxxxxxx;
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reg [31:0] x21 = 32'hxxxxxxxx;
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reg [31:0] x22 = 32'hxxxxxxxx;
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reg [31:0] x23 = 32'hxxxxxxxx;
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reg [31:0] x24 = 32'hxxxxxxxx;
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reg [31:0] x25 = 32'hxxxxxxxx;
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reg [31:0] x26 = 32'hxxxxxxxx;
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reg [31:0] x27 = 32'hxxxxxxxx;
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reg [31:0] x28 = 32'hxxxxxxxx;
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reg [31:0] x29 = 32'hxxxxxxxx;
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reg [31:0] x30 = 32'hxxxxxxxx;
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reg [31:0] x31 = 32'hxxxxxxxx;
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always @(posedge i_clk) begin
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update_rd <= i_cnt_done & i_wen0;
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if (i_wen0)
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dbg_rd <= {i_wdata0,dbg_rd[31:W]};
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//End of instruction that writes to RF
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if (update_rd) begin
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case (i_rd_addr)
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5'd1 : x1 <= dbg_rd;
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5'd2 : x2 <= dbg_rd;
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5'd3 : x3 <= dbg_rd;
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5'd4 : x4 <= dbg_rd;
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5'd5 : x5 <= dbg_rd;
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5'd6 : x6 <= dbg_rd;
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5'd7 : x7 <= dbg_rd;
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5'd8 : x8 <= dbg_rd;
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5'd9 : x9 <= dbg_rd;
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5'd10 : x10 <= dbg_rd;
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5'd11 : x11 <= dbg_rd;
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5'd12 : x12 <= dbg_rd;
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5'd13 : x13 <= dbg_rd;
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5'd14 : x14 <= dbg_rd;
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5'd15 : x15 <= dbg_rd;
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5'd16 : x16 <= dbg_rd;
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5'd17 : x17 <= dbg_rd;
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5'd18 : x18 <= dbg_rd;
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5'd19 : x19 <= dbg_rd;
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5'd20 : x20 <= dbg_rd;
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5'd21 : x21 <= dbg_rd;
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5'd22 : x22 <= dbg_rd;
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5'd23 : x23 <= dbg_rd;
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5'd24 : x24 <= dbg_rd;
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5'd25 : x25 <= dbg_rd;
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5'd26 : x26 <= dbg_rd;
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5'd27 : x27 <= dbg_rd;
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5'd28 : x28 <= dbg_rd;
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5'd29 : x29 <= dbg_rd;
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5'd30 : x30 <= dbg_rd;
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5'd31 : x31 <= dbg_rd;
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default : ;
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endcase
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end
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if (i_cnt_en)
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dbg_csr <= {i_csr_in, dbg_csr[31:W]};
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if (update_rd)
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if (i_csr_mstatus_en)
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dbg_mstatus <= dbg_csr;
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else if (i_csr_mie_en)
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dbg_mie <= dbg_csr;
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else if (i_csr_mcause_en)
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dbg_mcause <= dbg_csr;
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else if (i_csr_en)
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case (i_csr_addr)
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2'b00 : dbg_mscratch <= dbg_csr;
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2'b01 : dbg_mtvec <= dbg_csr;
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2'b10 : dbg_mepc <= dbg_csr;
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2'b11 : dbg_mtval <= dbg_csr;
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endcase
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end
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reg LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI,SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND, FENCE, ECALL, EBREAK;
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reg CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI;
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reg OTHER;
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always @(posedge i_clk) begin
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if (i_ibus_ack) begin
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LUI <= 1'b0;
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AUIPC <= 1'b0;
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JAL <= 1'b0;
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JALR <= 1'b0;
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BEQ <= 1'b0;
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BNE <= 1'b0;
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BLT <= 1'b0;
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BGE <= 1'b0;
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BLTU <= 1'b0;
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BGEU <= 1'b0;
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LB <= 1'b0;
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LH <= 1'b0;
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LW <= 1'b0;
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LBU <= 1'b0;
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LHU <= 1'b0;
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SB <= 1'b0;
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SH <= 1'b0;
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SW <= 1'b0;
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ADDI <= 1'b0;
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SLTI <= 1'b0;
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SLTIU <= 1'b0;
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XORI <= 1'b0;
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ORI <= 1'b0;
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ANDI <= 1'b0;
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SLLI <= 1'b0;
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SRLI <= 1'b0;
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SRAI <= 1'b0;
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ADD <= 1'b0;
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SUB <= 1'b0;
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SLL <= 1'b0;
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SLT <= 1'b0;
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SLTU <= 1'b0;
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XOR <= 1'b0;
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SRL <= 1'b0;
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SRA <= 1'b0;
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OR <= 1'b0;
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AND <= 1'b0;
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FENCE <= 1'b0;
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ECALL <= 1'b0;
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EBREAK <= 1'b0;
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CSRRW <= 1'b0;
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CSRRS <= 1'b0;
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CSRRC <= 1'b0;
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CSRRWI <= 1'b0;
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CSRRSI <= 1'b0;
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CSRRCI <= 1'b0;
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OTHER <= 1'b0;
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casez(i_ibus_rdt)
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// 3322222_22222 11111_111 11
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// 1098765_43210 98765_432 10987_65432_10
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32'b???????_?????_?????_???_?????_01101_11 : LUI <= 1'b1;
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32'b???????_?????_?????_???_?????_00101_11 : AUIPC <= 1'b1;
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32'b???????_?????_?????_???_?????_11011_11 : JAL <= 1'b1;
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32'b???????_?????_?????_000_?????_11001_11 : JALR <= 1'b1;
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32'b???????_?????_?????_000_?????_11000_11 : BEQ <= 1'b1;
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32'b???????_?????_?????_001_?????_11000_11 : BNE <= 1'b1;
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32'b???????_?????_?????_100_?????_11000_11 : BLT <= 1'b1;
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32'b???????_?????_?????_101_?????_11000_11 : BGE <= 1'b1;
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32'b???????_?????_?????_110_?????_11000_11 : BLTU <= 1'b1;
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32'b???????_?????_?????_111_?????_11000_11 : BGEU <= 1'b1;
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32'b???????_?????_?????_000_?????_00000_11 : LB <= 1'b1;
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32'b???????_?????_?????_001_?????_00000_11 : LH <= 1'b1;
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32'b???????_?????_?????_010_?????_00000_11 : LW <= 1'b1;
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32'b???????_?????_?????_100_?????_00000_11 : LBU <= 1'b1;
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32'b???????_?????_?????_101_?????_00000_11 : LHU <= 1'b1;
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32'b???????_?????_?????_000_?????_01000_11 : SB <= 1'b1;
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32'b???????_?????_?????_001_?????_01000_11 : SH <= 1'b1;
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32'b???????_?????_?????_010_?????_01000_11 : SW <= 1'b1;
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32'b???????_?????_?????_000_?????_00100_11 : ADDI <= 1'b1;
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32'b???????_?????_?????_010_?????_00100_11 : SLTI <= 1'b1;
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32'b???????_?????_?????_011_?????_00100_11 : SLTIU <= 1'b1;
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32'b???????_?????_?????_100_?????_00100_11 : XORI <= 1'b1;
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32'b???????_?????_?????_110_?????_00100_11 : ORI <= 1'b1;
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32'b???????_?????_?????_111_?????_00100_11 : ANDI <= 1'b1;
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32'b0000000_?????_?????_001_?????_00100_11 : SLLI <= 1'b1;
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32'b0000000_?????_?????_101_?????_00100_11 : SRLI <= 1'b1;
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32'b0100000_?????_?????_101_?????_00100_11 : SRAI <= 1'b1;
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32'b0000000_?????_?????_000_?????_01100_11 : ADD <= 1'b1;
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32'b0100000_?????_?????_000_?????_01100_11 : SUB <= 1'b1;
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32'b0000000_?????_?????_001_?????_01100_11 : SLL <= 1'b1;
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32'b0000000_?????_?????_010_?????_01100_11 : SLT <= 1'b1;
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32'b0000000_?????_?????_011_?????_01100_11 : SLTU <= 1'b1;
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32'b???????_?????_?????_100_?????_01100_11 : XOR <= 1'b1;
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32'b0000000_?????_?????_101_?????_01100_11 : SRL <= 1'b1;
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32'b0100000_?????_?????_101_?????_01100_11 : SRA <= 1'b1;
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32'b???????_?????_?????_110_?????_01100_11 : OR <= 1'b1;
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32'b???????_?????_?????_111_?????_01100_11 : AND <= 1'b1;
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32'b???????_?????_?????_000_?????_00011_11 : FENCE <= 1'b1;
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32'b0000000_00000_00000_000_00000_11100_11 : ECALL <= 1'b1;
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32'b0000000_00001_00000_000_00000_11100_11 : EBREAK <= 1'b1;
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32'b???????_?????_?????_001_?????_11100_11 : CSRRW <= 1'b1;
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32'b???????_?????_?????_010_?????_11100_11 : CSRRS <= 1'b1;
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32'b???????_?????_?????_011_?????_11100_11 : CSRRC <= 1'b1;
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32'b???????_?????_?????_101_?????_11100_11 : CSRRWI <= 1'b1;
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32'b???????_?????_?????_110_?????_11100_11 : CSRRSI <= 1'b1;
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32'b???????_?????_?????_111_?????_11100_11 : CSRRCI <= 1'b1;
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default : OTHER <= 1'b1;
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endcase
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end
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end
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`ifdef RISCV_FORMAL
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reg [31:0] pc = RESET_PC;
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wire rs_en = two_stage_op ? init : i_ctrl_pc_en;
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assign rvfi_rd_wdata = update_rd ? dbg_rd : 32'd0;
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always @(posedge i_clk) begin
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/* End of instruction */
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rvfi_valid <= i_cnt_done & i_ctrl_pc_en & !i_rst;
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rvfi_order <= rvfi_order + {63'd0,rvfi_valid};
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/* Get instruction word when it's fetched from ibus */
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if (i_ibus_cyc & i_ibus_ack)
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rvfi_insn <= i_ibus_rdt;
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if (i_cnt_done & i_ctrl_pc_en) begin
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rvfi_pc_rdata <= pc;
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if (!(rd_en & (|i_rd_addr))) begin
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rvfi_rd_addr <= 5'd0;
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end
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end
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rvfi_trap <= trap;
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if (rvfi_valid) begin
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rvfi_trap <= 1'b0;
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pc <= rvfi_pc_wdata;
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end
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/* RS1 not valid during J, U instructions (immdec_en[1]) */
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/* RS2 not valid during I, J, U instructions (immdec_en[2]) */
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if (i_rf_ready) begin
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rvfi_rs1_addr <= !immdec_en[1] ? rs1_addr : 5'd0;
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rvfi_rs2_addr <= !immdec_en[2] /*rs2_valid*/ ? rs2_addr : 5'd0;
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rvfi_rd_addr <= i_rd_addr;
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end
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if (rs_en) begin
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rvfi_rs1_rdata <= {(!immdec_en[1] ? rs1 : {W{1'b0}}),rvfi_rs1_rdata[31:W]};
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rvfi_rs2_rdata <= {(!immdec_en[2] ? rs2 : {W{1'b0}}),rvfi_rs2_rdata[31:W]};
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end
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if (i_dbus_ack) begin
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rvfi_mem_addr <= i_dbus_adr;
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rvfi_mem_rmask <= i_dbus_we ? 4'b0000 : i_dbus_sel;
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rvfi_mem_wmask <= i_dbus_we ? i_dbus_sel : 4'b0000;
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rvfi_mem_rdata <= i_dbus_rdt;
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rvfi_mem_wdata <= i_dbus_dat;
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end
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if (i_ibus_ack) begin
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rvfi_mem_rmask <= 4'b0000;
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rvfi_mem_wmask <= 4'b0000;
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end
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end
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assign rvfi_pc_wdata = i_ibus_adr;
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`endif
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endmodule
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