.. |
serv_aligner.v
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Compressed Extension for SERV
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2022-06-01 13:38:24 +02:00 |
serv_alu.v
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Rewrite logic expression of alu bool operations
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2021-05-15 23:07:55 +02:00 |
serv_bufreg.v
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Simplify optional MDU logic
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2021-10-03 23:28:45 +02:00 |
serv_bufreg2.v
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Move dbus_dat/rs2/shamt storage to bufreg2
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2022-01-02 22:10:33 +01:00 |
serv_compdec.v
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Compressed Extension for SERV
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2022-06-01 13:38:24 +02:00 |
serv_csr.v
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Add reset for mie_mtie
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2022-02-09 18:15:08 +01:00 |
serv_ctrl.v
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Expose with_csr in servant
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2022-07-26 00:28:53 +02:00 |
serv_decode.v
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Compressed Extension for SERV
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2022-06-01 13:38:24 +02:00 |
serv_immdec.v
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updated vars declaration for modelsim (#63)
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2021-10-03 23:15:54 +02:00 |
serv_mem_if.v
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Move dbus_dat/rs2/shamt storage to bufreg2
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2022-01-02 22:10:33 +01:00 |
serv_rf_if.v
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Expose with_csr in servant
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2022-07-26 00:28:53 +02:00 |
serv_rf_ram.v
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Always return 0 from reads to reg x0 in serv_rf_ram
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2021-08-27 13:10:06 +02:00 |
serv_rf_ram_if.v
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Remove unused wgo register
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2021-04-08 15:36:11 +02:00 |
serv_rf_top.v
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Update reamde, comments and paramters
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2022-06-13 10:38:11 +00:00 |
serv_state.v
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privilege tests fixed for rv32i
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2022-07-26 00:28:53 +02:00 |
serv_synth_wrapper.v
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Added openlane target and params.tcl with suitable openlane parameters for SERV
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2021-08-30 22:13:42 +02:00 |
serv_top.v
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Expose with_csr in servant
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2022-07-26 00:28:53 +02:00 |