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36 lines
612 B
Verilog
36 lines
612 B
Verilog
`default_nettype none
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module servus
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(input wire i_clk_p,
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input wire i_clk_n,
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output wire o_uart_tx,
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output wire q);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire i_clk;
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wire clk;
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wire rst;
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assign o_uart_tx = q;
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IBUFDS ibufds
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(.I (i_clk_p),
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.IB (i_clk_n),
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.O (i_clk));
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servus_clock_gen
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clock_gen
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(.i_clk (i_clk),
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.o_clk (clk),
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.o_rst (rst));
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (clk),
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.wb_rst (rst),
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.q (q));
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endmodule
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