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minor update

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This commit is contained in:
Blaise Tine 2021-07-20 21:42:22 -07:00
parent 8048796102
commit 0319283ea7
10 changed files with 51 additions and 50 deletions
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10
hw/rtl/VX_cluster.v
View file

@ -14,13 +14,13 @@ module VX_cluster #(
output wire mem_req_rw,
output wire [`L2MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`L2MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`L2MEM_LINE_WIDTH-1:0] mem_req_data,
output wire [`L2MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`L2MEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// Memory response
input wire mem_rsp_valid,
input wire [`L2MEM_LINE_WIDTH-1:0] mem_rsp_data,
input wire [`L2MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`L2MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
@ -33,12 +33,12 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_mem_req_rw;
wire [`NUM_CORES-1:0][`DMEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen;
wire [`NUM_CORES-1:0][`DMEM_ADDR_WIDTH-1:0] per_core_mem_req_addr;
wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_req_data;
wire [`NUM_CORES-1:0][`DMEM_DATA_WIDTH-1:0] per_core_mem_req_data;
wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag;
wire [`NUM_CORES-1:0] per_core_mem_req_ready;
wire [`NUM_CORES-1:0] per_core_mem_rsp_valid;
wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_rsp_data;
wire [`NUM_CORES-1:0][`DMEM_DATA_WIDTH-1:0] per_core_mem_rsp_data;
wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag;
wire [`NUM_CORES-1:0] per_core_mem_rsp_ready;
@ -145,7 +145,7 @@ module VX_cluster #(
VX_mem_arb #(
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`L2MEM_LINE_WIDTH),
.DATA_WIDTH (`L2MEM_DATA_WIDTH),
.ADDR_WIDTH (`L2MEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`XMEM_TAG_WIDTH),
.BUFFERED_REQ (1),

8
hw/rtl/VX_core.v
View file

@ -14,13 +14,13 @@ module VX_core #(
output wire mem_req_rw,
output wire [`DMEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`DMEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`DMEM_LINE_WIDTH-1:0] mem_req_data,
output wire [`DMEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// Memory reponse
input wire mem_rsp_valid,
input wire [`DMEM_LINE_WIDTH-1:0] mem_rsp_data,
input wire [`DMEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
@ -32,13 +32,13 @@ module VX_core #(
`endif
VX_mem_req_if #(
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.DATA_WIDTH (`DMEM_DATA_WIDTH),
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
) mem_req_if();
VX_mem_rsp_if #(
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.DATA_WIDTH (`DMEM_DATA_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
) mem_rsp_if();

10
hw/rtl/VX_define.vh
View file

@ -268,7 +268,7 @@
`define ICORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICORE_TAG_ID_BITS)
// Memory request data bits
`define IMEM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8)
`define IMEM_DATA_WIDTH (`ICACHE_LINE_SIZE * 8)
// Memory request address bits
`define IMEM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE))
@ -301,7 +301,7 @@
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
// Memory request data bits
`define DMEM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8)
`define DMEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8)
// Memory request address bits
`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE))
@ -346,7 +346,7 @@
`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
// Memory request data bits
`define L2MEM_LINE_WIDTH (`L2CACHE_LINE_SIZE * 8)
`define L2MEM_DATA_WIDTH (`L2CACHE_LINE_SIZE * 8)
// Memory request address bits
`define L2MEM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE))
@ -378,7 +378,7 @@
`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))
// Memory request data bits
`define L3MEM_LINE_WIDTH (`L3CACHE_LINE_SIZE * 8)
`define L3MEM_DATA_WIDTH (`L3CACHE_LINE_SIZE * 8)
// Memory request address bits
`define L3MEM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE))
@ -399,7 +399,7 @@
`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH
`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH
`define VX_MEM_LINE_WIDTH `L3MEM_LINE_WIDTH
`define VX_MEM_DATA_WIDTH `L3MEM_DATA_WIDTH
`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH
`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)

10
hw/rtl/VX_mem_unit.v
View file

@ -30,24 +30,24 @@ module VX_mem_unit # (
`endif
VX_mem_req_if #(
.LINE_WIDTH (`IMEM_LINE_WIDTH),
.DATA_WIDTH (`IMEM_DATA_WIDTH),
.ADDR_WIDTH (`IMEM_ADDR_WIDTH),
.TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_req_if();
VX_mem_rsp_if #(
.LINE_WIDTH (`IMEM_LINE_WIDTH),
.DATA_WIDTH (`IMEM_DATA_WIDTH),
.TAG_WIDTH (`IMEM_TAG_WIDTH)
) icache_mem_rsp_if();
VX_mem_req_if #(
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.DATA_WIDTH (`DMEM_DATA_WIDTH),
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_req_if();
VX_mem_rsp_if #(
.LINE_WIDTH (`DMEM_LINE_WIDTH),
.DATA_WIDTH (`DMEM_DATA_WIDTH),
.TAG_WIDTH (`DMEM_TAG_WIDTH)
) dcache_mem_rsp_if();
@ -271,7 +271,7 @@ module VX_mem_unit # (
VX_mem_arb #(
.NUM_REQS (2),
.DATA_WIDTH (`DMEM_LINE_WIDTH),
.DATA_WIDTH (`DMEM_DATA_WIDTH),
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
.BUFFERED_REQ (1),

10
hw/rtl/Vortex.v
View file

@ -12,13 +12,13 @@ module Vortex (
output wire mem_req_rw,
output wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`VX_MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`VX_MEM_LINE_WIDTH-1:0] mem_req_data,
output wire [`VX_MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`VX_MEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// Memory response
input wire mem_rsp_valid,
input wire [`VX_MEM_LINE_WIDTH-1:0] mem_rsp_data,
input wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
@ -31,12 +31,12 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw;
wire [`NUM_CLUSTERS-1:0][`L2MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
wire [`NUM_CLUSTERS-1:0][`L2MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
wire [`NUM_CLUSTERS-1:0][`L2MEM_LINE_WIDTH-1:0] per_cluster_mem_req_data;
wire [`NUM_CLUSTERS-1:0][`L2MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid;
wire [`NUM_CLUSTERS-1:0][`L2MEM_LINE_WIDTH-1:0] per_cluster_mem_rsp_data;
wire [`NUM_CLUSTERS-1:0][`L2MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready;
@ -143,7 +143,7 @@ module Vortex (
VX_mem_arb #(
.NUM_REQS (`NUM_CLUSTERS),
.DATA_WIDTH (`L3MEM_LINE_WIDTH),
.DATA_WIDTH (`L3MEM_DATA_WIDTH),
.ADDR_WIDTH (`L3MEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`L2MEM_TAG_WIDTH),
.BUFFERED_REQ (1),

36
hw/rtl/afu/vortex_afu.sv
View file

@ -37,17 +37,17 @@ module vortex_afu #(
input avs_readdatavalid [NUM_LOCAL_MEM_BANKS]
);
localparam LMEM_LINE_WIDTH = $bits(t_local_mem_data);
localparam LMEM_DATA_WIDTH = $bits(t_local_mem_data);
localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr);
localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt);
localparam CCI_LINE_WIDTH = $bits(t_ccip_clData);
localparam CCI_LINE_SIZE = CCI_LINE_WIDTH / 8;
localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_LINE_SIZE);
localparam CCI_DATA_WIDTH = $bits(t_ccip_clData);
localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8;
localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE);
localparam AVS_RD_QUEUE_SIZE = 4;
localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + $clog2(LMEM_LINE_WIDTH) - $clog2(`VX_MEM_LINE_WIDTH));
localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_LINE_WIDTH) - $clog2(CCI_LINE_WIDTH));
localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH));
localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH));
localparam AVS_REQ_TAGW = `MAX(AVS_REQ_TAGW_VX, AVS_REQ_TAGW_CCI);
localparam CCI_RD_WINDOW_SIZE = 8;
@ -77,7 +77,7 @@ localparam MMIO_DEV_CAPS = `AFU_IMAGE_MMIO_DEV_CAPS;
localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE;
localparam CCI_RD_QUEUE_TAGW = $clog2(CCI_RD_WINDOW_SIZE);
localparam CCI_RD_QUEUE_DATAW = CCI_LINE_WIDTH + CCI_ADDR_WIDTH;
localparam CCI_RD_QUEUE_DATAW = CCI_DATA_WIDTH + CCI_ADDR_WIDTH;
localparam STATE_IDLE = 0;
localparam STATE_WRITE = 1;
@ -102,12 +102,12 @@ wire vx_mem_req_valid;
wire vx_mem_req_rw;
wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen;
wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr;
wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_req_data;
wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_req_data;
wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag;
wire vx_mem_req_ready;
wire vx_mem_rsp_valid;
wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data;
wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data;
wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag;
wire vx_mem_rsp_ready;
@ -387,12 +387,12 @@ wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_dout;
wire cci_mem_req_valid;
wire cci_mem_req_rw;
wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_addr;
wire [CCI_LINE_WIDTH-1:0] cci_mem_req_data;
wire [CCI_DATA_WIDTH-1:0] cci_mem_req_data;
wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_tag;
wire cci_mem_req_ready;
wire cci_mem_rsp_valid;
wire [CCI_LINE_WIDTH-1:0] cci_mem_rsp_data;
wire [CCI_DATA_WIDTH-1:0] cci_mem_rsp_data;
wire [CCI_ADDR_WIDTH-1:0] cci_mem_rsp_tag;
wire cci_mem_rsp_ready;
@ -412,8 +412,8 @@ wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_arb_tag;
wire cci_mem_rsp_arb_ready;
VX_to_mem #(
.SRC_DATA_WIDTH (CCI_LINE_WIDTH),
.DST_DATA_WIDTH (LMEM_LINE_WIDTH),
.SRC_DATA_WIDTH (CCI_DATA_WIDTH),
.DST_DATA_WIDTH (LMEM_DATA_WIDTH),
.SRC_ADDR_WIDTH (CCI_ADDR_WIDTH),
.DST_ADDR_WIDTH (LMEM_ADDR_WIDTH),
.SRC_TAG_WIDTH (CCI_ADDR_WIDTH),
@ -425,7 +425,7 @@ VX_to_mem #(
.mem_req_valid_in (cci_mem_req_valid),
.mem_req_addr_in (cci_mem_req_addr),
.mem_req_rw_in (cci_mem_req_rw),
.mem_req_byteen_in ({CCI_LINE_SIZE{1'b1}}),
.mem_req_byteen_in ({CCI_DATA_SIZE{1'b1}}),
.mem_req_data_in (cci_mem_req_data),
.mem_req_tag_in (cci_mem_req_tag),
.mem_req_ready_in (cci_mem_req_ready),
@ -473,8 +473,8 @@ assign vx_mem_req_valid_qual = vx_mem_req_valid && vx_started;
assign vx_mem_req_ready = vx_mem_is_cout ? ~cout_q_full : vx_mem_req_ready_qual;
VX_to_mem #(
.SRC_DATA_WIDTH (`VX_MEM_LINE_WIDTH),
.DST_DATA_WIDTH (LMEM_LINE_WIDTH),
.SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
.DST_DATA_WIDTH (LMEM_DATA_WIDTH),
.SRC_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH),
.DST_ADDR_WIDTH (LMEM_ADDR_WIDTH),
.SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
@ -527,7 +527,7 @@ wire mem_rsp_ready;
VX_mem_arb #(
.NUM_REQS (2),
.DATA_WIDTH (LMEM_LINE_WIDTH),
.DATA_WIDTH (LMEM_DATA_WIDTH),
.ADDR_WIDTH (LMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (AVS_REQ_TAGW),
.BUFFERED_REQ (0),
@ -572,7 +572,7 @@ VX_mem_arb #(
VX_avs_wrapper #(
.NUM_BANKS (NUM_LOCAL_MEM_BANKS),
.AVS_DATA_WIDTH (LMEM_LINE_WIDTH),
.AVS_DATA_WIDTH (LMEM_DATA_WIDTH),
.AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH),
.AVS_BURST_WIDTH (LMEM_BURST_CTRW),
.AVS_BANKS (NUM_LOCAL_MEM_BANKS),

8
hw/rtl/interfaces/VX_mem_req_if.v
View file

@ -4,17 +4,17 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_req_if #(
parameter LINE_WIDTH = 1,
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter LINE_SIZE = LINE_WIDTH / 8
parameter DATA_SIZE = DATA_WIDTH / 8
) ();
wire valid;
wire rw;
wire [LINE_SIZE-1:0] byteen;
wire [DATA_SIZE-1:0] byteen;
wire [ADDR_WIDTH-1:0] addr;
wire [LINE_WIDTH-1:0] data;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;

4
hw/rtl/interfaces/VX_mem_rsp_if.v
View file

@ -4,12 +4,12 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_rsp_if #(
parameter LINE_WIDTH = 1,
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [LINE_WIDTH-1:0] data;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;

3
hw/syn/opae/.gitignore vendored
View file

@ -1,2 +1 @@
build_ase*/
build_fpga*/
build_*/

2
hw/syn/quartus/project.tcl
View file

@ -42,7 +42,9 @@ set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name SEED 1
# Power estimation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"