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popcount specialization
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Blaise Tine
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2 changed files with 141 additions and 0 deletions
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@ -1,6 +1,77 @@
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_popcount63(
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input wire [5:0] data_in,
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output wire [2:0] data_out
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);
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reg [2:0] sum;
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always @(*) begin
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case (data_in)
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6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2;
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6'd4: sum=3'd1; 6'd5: sum=3'd2; 6'd6: sum=3'd2; 6'd7: sum=3'd3;
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6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3;
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6'd12: sum=3'd2; 6'd13: sum=3'd3; 6'd14: sum=3'd3; 6'd15: sum=3'd4;
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6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3;
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6'd20: sum=3'd2; 6'd21: sum=3'd3; 6'd22: sum=3'd3; 6'd23: sum=3'd4;
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6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4;
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6'd28: sum=3'd3; 6'd29: sum=3'd4; 6'd30: sum=3'd4; 6'd31: sum=3'd5;
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6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3;
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6'd36: sum=3'd2; 6'd37: sum=3'd3; 6'd38: sum=3'd3; 6'd39: sum=3'd4;
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6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4;
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6'd44: sum=3'd3; 6'd45: sum=3'd4; 6'd46: sum=3'd4; 6'd47: sum=3'd5;
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6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4;
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6'd52: sum=3'd3; 6'd53: sum=3'd4; 6'd54: sum=3'd4; 6'd55: sum=3'd5;
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6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5;
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6'd60: sum=3'd4; 6'd61: sum=3'd5; 6'd62: sum=3'd5; 6'd63: sum=3'd6;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_popcount32(
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input wire [2:0] data_in,
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output wire [1:0] data_out
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);
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reg [1:0] sum;
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always @(*) begin
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case (data_in)
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3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2;
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3'd4: sum=2'd1; 3'd5: sum=2'd2; 3'd6: sum=2'd2; 3'd7: sum=2'd3;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_sum33(
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input wire [2:0] data_in1,
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input wire [2:0] data_in2,
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output wire [3:0] data_out
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);
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reg [3:0] sum;
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always @(*) begin
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case ({data_in1, data_in2})
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6'd0: sum=4'd0; 6'd1: sum=4'd1; 6'd2: sum=4'd2; 6'd3: sum=4'd3;
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6'd4: sum=4'd4; 6'd5: sum=4'd5; 6'd6: sum=4'd6; 6'd7: sum=4'd7;
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6'd8: sum=4'd1; 6'd9: sum=4'd2; 6'd10: sum=4'd3; 6'd11: sum=4'd4;
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6'd12: sum=4'd5; 6'd13: sum=4'd6; 6'd14: sum=4'd7; 6'd15: sum=4'd8;
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6'd16: sum=4'd2; 6'd17: sum=4'd3; 6'd18: sum=4'd4; 6'd19: sum=4'd5;
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6'd20: sum=4'd6; 6'd21: sum=4'd7; 6'd22: sum=4'd8; 6'd23: sum=4'd9;
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6'd24: sum=4'd3; 6'd25: sum=4'd4; 6'd26: sum=4'd5; 6'd27: sum=4'd6;
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6'd28: sum=4'd7; 6'd29: sum=4'd8; 6'd30: sum=4'd9; 6'd31: sum=4'd10;
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6'd32: sum=4'd4; 6'd33: sum=4'd5; 6'd34: sum=4'd6; 6'd35: sum=4'd7;
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6'd36: sum=4'd8; 6'd37: sum=4'd9; 6'd38: sum=4'd10; 6'd39: sum=4'd11;
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6'd40: sum=4'd5; 6'd41: sum=4'd6; 6'd42: sum=4'd7; 6'd43: sum=4'd8;
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6'd44: sum=4'd9; 6'd45: sum=4'd10; 6'd46: sum=4'd11; 6'd47: sum=4'd12;
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6'd48: sum=4'd6; 6'd49: sum=4'd7; 6'd50: sum=4'd8; 6'd51: sum=4'd9;
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6'd52: sum=4'd10; 6'd53: sum=4'd11; 6'd54: sum=4'd12; 6'd55: sum=4'd13;
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6'd56: sum=4'd7; 6'd57: sum=4'd8; 6'd58: sum=4'd9; 6'd59: sum=4'd10;
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6'd60: sum=4'd11; 6'd61: sum=4'd12; 6'd62: sum=4'd13; 6'd63: sum=4'd14;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_popcount #(
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parameter MODEL = 1,
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parameter N = 1,
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@ -20,6 +91,73 @@ module VX_popcount #(
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assign data_out = data_in;
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end else if (N <= 3) begin
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reg [2:0] t_in;
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wire [1:0] t_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount32 pc32(t_in, t_out);
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assign data_out = t_out[M-1:0];
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end else if (N <= 6) begin
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reg [5:0] t_in;
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wire [2:0] t_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63(t_in, t_out);
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assign data_out = t_out[M-1:0];
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end else if (N <= 9) begin
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reg [8:0] t_in;
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wire [4:0] t1_out;
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wire [3:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63(t_in[5:0], t1_out[2:0]);
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VX_popcount32 pc32(t_in[8:6], t1_out[4:3]);
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VX_sum33 sum33(t1_out[2:0], {1'b0, t1_out[4:3]}, t2_out);
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assign data_out = t2_out[M-1:0];
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end else if (N <= 12) begin
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reg [11:0] t_in;
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wire [5:0] t1_out;
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wire [3:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]);
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VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]);
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VX_sum33 sum33(t1_out[2:0], t1_out[5:3], t2_out);
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assign data_out = t2_out[M-1:0];
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end else if (N <= 18) begin
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reg [17:0] t_in;
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wire [8:0] t1_out;
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wire [4:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]);
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VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]);
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VX_popcount63 pc63c(t_in[17:12], t1_out[8:6]);
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VX_popcount32 pc32a({t1_out[0], t1_out[3], t1_out[6]}, t2_out[1:0]);
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VX_popcount32 pc32b({t1_out[1], t1_out[4], t1_out[7]}, t2_out[3:2]);
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VX_popcount32 pc32c({t1_out[2], t1_out[5], t1_out[8]}, t2_out[4:3]);
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assign data_out = {2'b0,t2_out[1:0]} + {1'b0,t2_out[3:2],1'b0} + {t2_out[4:3],2'b0};
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end else if (MODEL == 1) begin
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localparam PN = 1 << $clog2(N);
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@ -39,8 +39,11 @@ TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=
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TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
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TARGET=hw PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
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TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo
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FPGA_BIN_DIR=<bin_dir> TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
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FPGA_BIN_DIR=<bin_dir> TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo
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# build report logs
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<build_dir>/bin/vortex_afu.xclbin.info
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<build_dir>/_x/reports/link/syn/ulp_vortex_afu_1_0_synth_1_ulp_vortex_afu_1_0_utilization_synth.rpt
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<build_dir>/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log
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<build_dir>/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt
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