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fixed xilinx synthesis issue with struct input/output signals

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This commit is contained in:
Blaise Tine 2023-03-21 04:45:19 -04:00
parent db9f424a64
commit 52b0765726
8 changed files with 16 additions and 27 deletions
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2
hw/rtl/fpu_unit/VX_fpu_cvt.sv
View file

@ -24,7 +24,7 @@ module VX_fpu_cvt #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,

10
hw/rtl/fpu_unit/VX_fpu_div.sv
View file

@ -19,7 +19,7 @@ module VX_fpu_div #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,
@ -77,12 +77,8 @@ module VX_fpu_div #(
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;
assign fflags[i].UF = tuser[0];
assign fflags[i].OF = tuser[1];
assign fflags[i].DZ = tuser[3];
assign fflags[i].NV = tuser[2];
// NV, DZ, OF, UF, NX
assign fflags = {tuser[2], tuser[3], tuser[1], tuser[0], 1'b0};
end
assign has_fflags = 1;

2
hw/rtl/fpu_unit/VX_fpu_dpi.sv
View file

@ -22,7 +22,7 @@ module VX_fpu_dpi #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,

10
hw/rtl/fpu_unit/VX_fpu_fma.sv
View file

@ -24,7 +24,7 @@ module VX_fpu_fma #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,
@ -107,12 +107,8 @@ module VX_fpu_fma #(
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;
assign fflags[i].UF = tuser[0];
assign fflags[i].OF = tuser[1];
assign fflags[i].DZ = 1'b0;
assign fflags[i].NV = tuser[2];
// NV, DZ, OF, UF, NX
assign fflags = {tuser[2], 1'b0, tuser[1], tuser[0], 1'b0};
end
`else

2
hw/rtl/fpu_unit/VX_fpu_fpga.sv
View file

@ -21,7 +21,7 @@ module VX_fpu_fpga #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,

2
hw/rtl/fpu_unit/VX_fpu_fpnew.sv
View file

@ -30,7 +30,7 @@ module VX_fpu_fpnew #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,

5
hw/rtl/fpu_unit/VX_fpu_ncomp.sv
View file

@ -23,7 +23,7 @@ module VX_fpu_ncomp #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,
@ -269,7 +269,8 @@ module VX_fpu_ncomp #(
assign ready_in = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign fflags[i] = {fflags_NV[i], 4'b0};
// NV, DZ, OF, UF, NX
assign fflags[i] = {fflags_NV[i], 1'b0, 1'b0, 1'b0, 1'b0};
end
endmodule

10
hw/rtl/fpu_unit/VX_fpu_sqrt.sv
View file

@ -18,7 +18,7 @@ module VX_fpu_sqrt #(
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags,
output wire [TAGW-1:0] tag_out,
@ -71,12 +71,8 @@ module VX_fpu_sqrt #(
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;
assign fflags[i].UF = 1'b0;
assign fflags[i].OF = 1'b0;
assign fflags[i].DZ = 1'b0;
assign fflags[i].NV = tuser;
// NV, DZ, OF, UF, NX
assign fflags = {tuser, 1'b0, 1'b0, 1'b0, 1'b0};
end
`else