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renamed texture bus interface

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This commit is contained in:
Blaise Tine 2023-06-22 11:53:06 -04:00
parent 668487088f
commit 09dcf6f4b2
16 changed files with 176 additions and 250 deletions
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30
hw/rtl/VX_cluster.sv
View file

@ -248,25 +248,15 @@ module VX_cluster #(
.TAG_WIDTH (TCACHE_TAG_WIDTH)
) tcache_bus_if[`NUM_TEX_UNITS]();
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB1_TAG_WIDTH)
) per_socket_tex_req_if[`NUM_SOCKETS]();
) per_socket_tex_bus_if[`NUM_SOCKETS]();
VX_tex_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB1_TAG_WIDTH)
) per_socket_tex_rsp_if[`NUM_SOCKETS]();
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB2_TAG_WIDTH)
) tex_req_if[`NUM_TEX_UNITS]();
VX_tex_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB2_TAG_WIDTH)
) tex_rsp_if[`NUM_TEX_UNITS]();
) tex_bus_if[`NUM_TEX_UNITS]();
`RESET_RELAY (tex_arb_reset, reset);
@ -280,10 +270,8 @@ module VX_cluster #(
) tex_arb (
.clk (clk),
.reset (tex_arb_reset),
.req_in_if (per_socket_tex_req_if),
.rsp_in_if (per_socket_tex_rsp_if),
.req_out_if (tex_req_if),
.rsp_out_if (tex_rsp_if)
.bus_in_if (per_socket_tex_bus_if),
.bus_out_if (tex_bus_if)
);
VX_dcr_write_if tex_dcr_write_tmp_if();
@ -309,8 +297,7 @@ module VX_cluster #(
.perf_tex_if (perf_tex_unit_if[i]),
`endif
.dcr_write_if (tex_dcr_write_if),
.tex_req_if (tex_req_if[i]),
.tex_rsp_if (tex_rsp_if[i]),
.tex_bus_if (tex_bus_if[i]),
.cache_bus_if (tcache_bus_if[i])
);
end
@ -465,8 +452,7 @@ module VX_cluster #(
.perf_tex_if (perf_tex_total_if),
.perf_tcache_if (perf_tcache_total_if),
`endif
.tex_req_if (per_socket_tex_req_if[i]),
.tex_rsp_if (per_socket_tex_rsp_if[i]),
.tex_bus_if (per_socket_tex_bus_if[i]),
`endif
`ifdef EXT_RASTER_ENABLE

26
hw/rtl/VX_define.vh
View file

@ -400,20 +400,18 @@
assign dst.face = src.face; \
assign src.ready = dst.ready
`define ASSIGN_VX_TEX_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.mask = src.mask; \
assign dst.coords= src.coords; \
assign dst.lod = src.lod; \
assign dst.stage = src.stage; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_TEX_RSP_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.texels= src.texels; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_TEX_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_mask = src.req_mask; \
assign dst.req_coords= src.req_coords; \
assign dst.req_lod = src.req_lod; \
assign dst.req_stage = src.req_stage; \
assign dst.req_tag = src.req_tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_texels= dst.rsp_texels; \
assign src.rsp_tag = dst.rsp_tag; \
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_FPU_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \

32
hw/rtl/VX_socket.sv
View file

@ -33,8 +33,7 @@ module VX_socket #(
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
`endif
VX_tex_req_if.master tex_req_if,
VX_tex_rsp_if.slave tex_rsp_if,
VX_tex_bus_if.master tex_bus_if,
`endif
`ifdef EXT_RASTER_ENABLE
@ -129,25 +128,15 @@ module VX_socket #(
`ifdef EXT_TEX_ENABLE
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
) per_core_tex_req_if[`SOCKET_SIZE]();
) per_core_tex_bus_if[`SOCKET_SIZE]();
VX_tex_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
) per_core_tex_rsp_if[`SOCKET_SIZE]();
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB1_TAG_WIDTH)
) tex_req_tmp_if[1]();
VX_tex_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_ARB1_TAG_WIDTH)
) tex_rsp_tmp_if[1]();
) tex_bus_tmp_if[1]();
`RESET_RELAY (tex_arb_reset, reset);
@ -161,13 +150,11 @@ module VX_socket #(
) tex_arb (
.clk (clk),
.reset (tex_arb_reset),
.req_in_if (per_core_tex_req_if),
.rsp_in_if (per_core_tex_rsp_if),
.req_out_if (tex_req_tmp_if),
.rsp_out_if (tex_rsp_tmp_if)
.bus_in_if (per_core_tex_bus_if),
.bus_out_if (tex_bus_tmp_if)
);
`ASSIGN_VX_TEX_REQ_IF (tex_req_if, tex_req_tmp_if[0]);
`ASSIGN_VX_TEX_BUS_IF (tex_bus_if, tex_bus_tmp_if[0]);
`endif
@ -320,8 +307,7 @@ module VX_socket #(
.perf_tex_if (perf_tex_if),
.perf_tcache_if (perf_tcache_if),
`endif
.tex_req_if (per_core_tex_req_if[i]),
.tex_rsp_if (per_core_tex_rsp_if[i]),
.tex_bus_if (per_core_tex_bus_if[i]),
`endif
`ifdef EXT_RASTER_ENABLE

6
hw/rtl/cache/VX_cache.sv vendored
View file

@ -113,7 +113,7 @@ module VX_cache #(
.reset (core_rsp_reset),
.valid_in (core_rsp_valid_s[i]),
.ready_in (core_rsp_ready_s[i]),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_out ({core_bus_if[i].rsp_data, core_bus_if[i].rsp_tag}),
.valid_out (core_bus_if[i].rsp_valid),
.ready_out (core_bus_if[i].rsp_ready)
@ -140,7 +140,7 @@ module VX_cache #(
.reset (reset),
.valid_in (mem_req_valid_s),
.ready_in (mem_req_ready_s),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_out ({mem_bus_if.req_rw, mem_bus_if.req_byteen, mem_bus_if.req_addr, mem_bus_if.req_data, mem_bus_if.req_tag}),
.valid_out (mem_bus_if.req_valid),
.ready_out (mem_bus_if.req_ready)
@ -164,7 +164,7 @@ module VX_cache #(
.valid_in (mem_bus_if.rsp_valid),
.ready_in (mem_bus_if.rsp_ready),
.data_in ({mem_bus_if.rsp_tag, mem_bus_if.rsp_data}),
.data_out ({mem_rsp_tag_s, mem_rsp_data_s}),
.data_out ({mem_rsp_tag_s, mem_rsp_data_s}),
.valid_out (mem_rsp_valid_s),
.ready_out (mem_rsp_ready_s)
);

4
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -119,7 +119,7 @@ module VX_cache_wrap #(
.reset (core_rsp_reset),
.valid_in (core_rsp_valid_s[i]),
.ready_in (core_rsp_ready_s[i]),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_out ({core_bus_if[i].rsp_data, core_bus_if[i].rsp_tag}),
.valid_out (core_bus_if[i].rsp_valid),
.ready_out (core_bus_if[i].rsp_ready)
@ -146,7 +146,7 @@ module VX_cache_wrap #(
.reset (reset),
.valid_in (mem_req_valid_s),
.ready_in (mem_req_ready_s),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_out ({mem_bus_if.req_rw, mem_bus_if.req_byteen, mem_bus_if.req_addr, mem_bus_if.req_data, mem_bus_if.req_tag}),
.valid_out (mem_bus_if.req_valid),
.ready_out (mem_bus_if.req_ready)

40
hw/rtl/core/VX_core.sv
View file

@ -52,8 +52,7 @@ module VX_core #(
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
`endif
VX_tex_req_if.master tex_req_if,
VX_tex_rsp_if.slave tex_rsp_if,
VX_tex_bus_if.master tex_bus_if,
`endif
`ifdef EXT_RASTER_ENABLE
@ -207,8 +206,7 @@ module VX_core #(
`endif
`ifdef EXT_TEX_ENABLE
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if),
.tex_bus_if (tex_bus_if),
`ifdef PERF_ENABLE
.perf_tex_if (perf_tex_if),
.perf_tcache_if (perf_tcache_if),
@ -536,28 +534,23 @@ module VX_core_top #(
`endif
`ifdef EXT_TEX_ENABLE
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
) tex_req_if();
) tex_bus_if();
VX_tex_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
) tex_rsp_if();
assign tex_req_valid = tex_bus_if.req_req_valid;
assign tex_req_mask = tex_bus_if.req_req_mask;
assign tex_req_coords = tex_bus_if.req_req_coords;
assign tex_req_lod = tex_bus_if.req_req_lod;
assign tex_req_stage = tex_bus_if.req_req_stage;
assign tex_req_tag = tex_bus_if.req_req_tag;
assign tex_bus_if.req_req_ready = tex_req_ready;
assign tex_req_valid = tex_req_if.valid;
assign tex_req_mask = tex_req_if.mask;
assign tex_req_coords = tex_req_if.coords;
assign tex_req_lod = tex_req_if.lod;
assign tex_req_stage = tex_req_if.stage;
assign tex_req_tag = tex_req_if.tag;
assign tex_req_if.ready = tex_req_ready;
assign tex_rsp_if.valid = tex_rsp_valid;
assign tex_rsp_if.texels = tex_rsp_texels;
assign tex_rsp_if.tag = tex_rsp_tag;
assign tex_rsp_ready = tex_rsp_if.ready;
assign tex_bus_if.rsp_valid = tex_rsp_valid;
assign tex_bus_if.rsp_texels = tex_rsp_texels;
assign tex_bus_if.rsp_tag = tex_rsp_tag;
assign tex_rsp_ready = tex_bus_if.rsp_ready;
`endif
`ifdef EXT_RASTER_ENABLE
@ -612,8 +605,7 @@ module VX_core_top #(
`endif
`ifdef EXT_TEX_ENABLE
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if),
.tex_bus_if (tex_bus_if),
`endif
`ifdef EXT_RASTER_ENABLE

6
hw/rtl/core/VX_execute.sv
View file

@ -36,8 +36,7 @@ module VX_execute #(
`endif
`ifdef EXT_TEX_ENABLE
VX_tex_req_if.master tex_req_if,
VX_tex_rsp_if.slave tex_rsp_if,
VX_tex_bus_if.master tex_bus_if,
`ifdef PERF_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
@ -215,8 +214,7 @@ module VX_execute #(
`ifdef EXT_TEX_ENABLE
.tex_csr_if (tex_csr_if),
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if),
.tex_bus_if (tex_bus_if),
`endif
`ifdef EXT_RASTER_ENABLE

6
hw/rtl/core/VX_gpu_unit.sv
View file

@ -20,8 +20,7 @@ module VX_gpu_unit #(
`ifdef EXT_TEX_ENABLE
VX_gpu_csr_if.slave tex_csr_if,
VX_tex_req_if.master tex_req_if,
VX_tex_rsp_if.slave tex_rsp_if,
VX_tex_bus_if.master tex_bus_if,
`endif
`ifdef EXT_RASTER_ENABLE
@ -177,8 +176,7 @@ module VX_gpu_unit #(
.tex_csr_if (tex_csr_if),
.tex_agent_if (tex_agent_if),
.tex_commit_if (tex_commit_if),
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if)
.tex_bus_if (tex_bus_if)
);
assign rsp_arb_valid_in[RSP_ARB_IDX_TEX] = tex_commit_if.valid;

2
hw/rtl/core/VX_icache_stage.sv
View file

@ -93,7 +93,7 @@ module VX_icache_stage #(
.reset (reset),
.valid_in (icache_req_valid),
.ready_in (icache_req_ready),
.data_in ({icache_req_addr, icache_req_tag}),
.data_in ({icache_req_addr, icache_req_tag}),
.data_out ({icache_bus_if.req_addr, icache_bus_if.req_tag}),
.valid_out (icache_bus_if.req_valid),
.ready_out (icache_bus_if.req_ready)

4
hw/rtl/fpu/VX_fpu_agent.sv
View file

@ -80,8 +80,8 @@ module VX_fpu_agent #(
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in ({fpu_agent_if.op_type, fpu_agent_if.fmt, req_op_frm, fpu_agent_if.rs1_data, fpu_agent_if.rs2_data, fpu_agent_if.rs3_data, req_tag}),
.data_out ({fpu_bus_if.req_type, fpu_bus_if.req_fmt, fpu_bus_if.req_frm, fpu_bus_if.req_dataa, fpu_bus_if.req_datab, fpu_bus_if.req_datac, fpu_bus_if.req_tag}),
.data_in ({fpu_agent_if.op_type, fpu_agent_if.fmt, req_op_frm, fpu_agent_if.rs1_data, fpu_agent_if.rs2_data, fpu_agent_if.rs3_data, req_tag}),
.data_out ({fpu_bus_if.req_type, fpu_bus_if.req_fmt, fpu_bus_if.req_frm, fpu_bus_if.req_dataa, fpu_bus_if.req_datab, fpu_bus_if.req_datac, fpu_bus_if.req_tag}),
.valid_out (fpu_bus_if.req_valid),
.ready_out (fpu_bus_if.req_ready)
);

25
hw/rtl/tex/VX_tex_agent.sv
View file

@ -8,11 +8,10 @@ module VX_tex_agent #(
// Inputs
VX_gpu_csr_if.slave tex_csr_if,
VX_tex_agent_if.slave tex_agent_if,
VX_tex_rsp_if.slave tex_rsp_if,
VX_tex_agent_if.slave tex_agent_if,
// Outputs
VX_tex_req_if.master tex_req_if,
VX_tex_bus_if.master tex_bus_if,
VX_commit_if.master tex_commit_if
);
`UNUSED_PARAM (CORE_ID)
@ -53,7 +52,7 @@ module VX_tex_agent #(
wire mdata_full;
wire mdata_push = tex_agent_if.valid && tex_agent_if.ready;
wire mdata_pop = tex_rsp_if.valid && tex_rsp_if.ready;
wire mdata_pop = tex_bus_if.rsp_valid && tex_bus_if.rsp_ready;
VX_index_buffer #(
.DATAW (NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS),
@ -88,25 +87,25 @@ module VX_tex_agent #(
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in ({tex_agent_if.tmask, tex_agent_if.coords, tex_agent_if.lod, tex_agent_if.stage, req_tag}),
.data_out ({tex_req_if.mask, tex_req_if.coords, tex_req_if.lod, tex_req_if.stage, tex_req_if.tag}),
.valid_out (tex_req_if.valid),
.ready_out (tex_req_if.ready)
.data_in ({tex_agent_if.tmask, tex_agent_if.coords, tex_agent_if.lod, tex_agent_if.stage, req_tag}),
.data_out ({tex_bus_if.req_mask, tex_bus_if.req_coords, tex_bus_if.req_lod, tex_bus_if.req_stage, tex_bus_if.req_tag}),
.valid_out (tex_bus_if.req_valid),
.ready_out (tex_bus_if.req_ready)
);
// handle texture response
assign mdata_raddr = tex_rsp_if.tag[0 +: REQ_QUEUE_BITS];
assign rsp_uuid = tex_rsp_if.tag[REQ_QUEUE_BITS +: UUID_WIDTH];
assign mdata_raddr = tex_bus_if.rsp_tag[0 +: REQ_QUEUE_BITS];
assign rsp_uuid = tex_bus_if.rsp_tag[REQ_QUEUE_BITS +: UUID_WIDTH];
VX_skid_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + (`NUM_THREADS * 32))
) rsp_sbuf (
.clk (clk),
.reset (reset),
.valid_in (tex_rsp_if.valid),
.ready_in (tex_rsp_if.ready),
.data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, tex_rsp_if.texels}),
.valid_in (tex_bus_if.rsp_valid),
.ready_in (tex_bus_if.rsp_ready),
.data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, tex_bus_if.rsp_texels}),
.data_out ({tex_commit_if.uuid, tex_commit_if.wid, tex_commit_if.tmask, tex_commit_if.PC, tex_commit_if.rd, tex_commit_if.data}),
.valid_out (tex_commit_if.valid),
.ready_out (tex_commit_if.ready)

51
hw/rtl/tex/VX_tex_arb.sv
View file

@ -13,17 +13,8 @@ module VX_tex_arb #(
input wire clk,
input wire reset,
// input requests
VX_tex_req_if.slave req_in_if [NUM_INPUTS],
// input responses
VX_tex_rsp_if.master rsp_in_if [NUM_INPUTS],
// output request
VX_tex_req_if.master req_out_if [NUM_OUTPUTS],
// output response
VX_tex_rsp_if.slave rsp_out_if [NUM_OUTPUTS]
VX_tex_bus_if.slave bus_in_if [NUM_INPUTS],
VX_tex_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS);
@ -44,8 +35,8 @@ module VX_tex_arb #(
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign req_valid_in[i] = req_in_if[i].valid;
assign req_in_if[i].ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign bus_in_if[i].req_ready = req_ready_in[i];
if (NUM_INPUTS > NUM_OUTPUTS) begin
wire [TAG_OUT_WIDTH-1:0] req_tag_in;
@ -55,13 +46,13 @@ module VX_tex_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_insert (
.data_in (req_in_if[i].tag),
.data_in (bus_in_if[i].req_tag),
.sel_in (LOG_NUM_REQS'(r)),
.data_out (req_tag_in)
);
assign req_data_in[i] = {req_tag_in, req_in_if[i].mask, req_in_if[i].coords, req_in_if[i].lod, req_in_if[i].stage};
assign req_data_in[i] = {req_tag_in, bus_in_if[i].req_mask, bus_in_if[i].req_coords, bus_in_if[i].req_lod, bus_in_if[i].req_stage};
end else begin
assign req_data_in[i] = {req_in_if[i].tag, req_in_if[i].mask, req_in_if[i].coords, req_in_if[i].lod, req_in_if[i].stage};
assign req_data_in[i] = {bus_in_if[i].req_tag, bus_in_if[i].req_mask, bus_in_if[i].req_coords, bus_in_if[i].req_lod, bus_in_if[i].req_stage};
end
end
@ -84,9 +75,9 @@ module VX_tex_arb #(
);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign req_out_if[i].valid = req_valid_out[i];
assign {req_out_if[i].tag, req_out_if[i].mask, req_out_if[i].coords, req_out_if[i].lod, req_out_if[i].stage} = req_data_out[i];
assign req_ready_out[i] = req_out_if[i].ready;
assign bus_out_if[i].req_valid = req_valid_out[i];
assign {bus_out_if[i].req_tag, bus_out_if[i].req_mask, bus_out_if[i].req_coords, bus_out_if[i].req_lod, bus_out_if[i].req_stage} = req_data_out[i];
assign req_ready_out[i] = bus_out_if[i].req_ready;
end
///////////////////////////////////////////////////////////////////////////
@ -111,16 +102,16 @@ module VX_tex_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_remove (
.data_in (rsp_out_if[i].tag),
.data_in (bus_out_if[i].rsp_tag),
.data_out (rsp_tag_out)
);
assign rsp_valid_in[i] = rsp_out_if[i].valid;
assign rsp_data_in[i] = {rsp_tag_out, rsp_out_if[i].texels};
assign rsp_out_if[i].ready = rsp_ready_in[i];
assign rsp_valid_in[i] = bus_out_if[i].rsp_valid;
assign rsp_data_in[i] = {rsp_tag_out, bus_out_if[i].rsp_texels};
assign bus_out_if[i].rsp_ready = rsp_ready_in[i];
if (NUM_INPUTS > 1) begin
assign rsp_sel_in[i] = rsp_out_if[i].tag[TAG_SEL_IDX +: LOG_NUM_REQS];
assign rsp_sel_in[i] = bus_out_if[i].rsp_tag[TAG_SEL_IDX +: LOG_NUM_REQS];
end else begin
assign rsp_sel_in[i] = '0;
end
@ -147,9 +138,9 @@ module VX_tex_arb #(
end else begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign rsp_valid_in[i] = rsp_out_if[i].valid;
assign rsp_data_in[i] = {rsp_out_if[i].tag, rsp_out_if[i].texels};
assign rsp_out_if[i].ready = rsp_ready_in[i];
assign rsp_valid_in[i] = bus_out_if[i].rsp_valid;
assign rsp_data_in[i] = {bus_out_if[i].rsp_tag, bus_out_if[i].rsp_texels};
assign bus_out_if[i].rsp_ready = rsp_ready_in[i];
end
VX_stream_arb #(
@ -173,9 +164,9 @@ module VX_tex_arb #(
end
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign rsp_in_if[i].valid = rsp_valid_out[i];
assign {rsp_in_if[i].tag,rsp_in_if[i].texels} = rsp_data_out[i];
assign rsp_ready_out[i] = rsp_in_if[i].ready;
assign bus_in_if[i].rsp_valid = rsp_valid_out[i];
assign {bus_in_if[i].rsp_tag,bus_in_if[i].rsp_texels} = rsp_data_out[i];
assign rsp_ready_out[i] = bus_in_if[i].rsp_ready;
end
endmodule

51
hw/rtl/tex/VX_tex_bus_if.sv Normal file
View file

@ -0,0 +1,51 @@
`include "VX_tex_define.vh"
interface VX_tex_bus_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire req_valid;
wire [NUM_LANES-1:0] req_mask;
wire [1:0][NUM_LANES-1:0][31:0] req_coords;
wire [NUM_LANES-1:0][`TEX_LOD_BITS-1:0] req_lod;
wire [`TEX_STAGE_BITS-1:0] req_stage;
wire [TAG_WIDTH-1:0] req_tag;
wire req_ready;
wire rsp_valid;
wire [NUM_LANES-1:0][31:0] rsp_texels;
wire [TAG_WIDTH-1:0] rsp_tag;
wire rsp_ready;
modport master (
output req_valid,
output req_mask,
output req_coords,
output req_lod,
output req_stage,
output req_tag,
input req_ready,
input rsp_valid,
input rsp_texels,
input rsp_tag,
output rsp_ready
);
modport slave (
input req_valid,
input req_mask,
input req_coords,
input req_lod,
input req_stage,
input req_tag,
output req_ready,
output rsp_valid,
output rsp_texels,
output rsp_tag,
input rsp_ready
);
endinterface

36
hw/rtl/tex/VX_tex_req_if.sv
View file

@ -1,36 +0,0 @@
`include "VX_tex_define.vh"
interface VX_tex_req_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_LANES-1:0] mask;
wire [1:0][NUM_LANES-1:0][31:0] coords;
wire [NUM_LANES-1:0][`TEX_LOD_BITS-1:0] lod;
wire [`TEX_STAGE_BITS-1:0] stage;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output mask,
output coords,
output lod,
output stage,
output tag,
input ready
);
modport slave (
input valid,
input mask,
input coords,
input lod,
input stage,
input tag,
output ready
);
endinterface

27
hw/rtl/tex/VX_tex_rsp_if.sv
View file

@ -1,27 +0,0 @@
`include "VX_tex_define.vh"
interface VX_tex_rsp_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_LANES-1:0][31:0] texels;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output texels,
output tag,
input ready
);
modport slave (
input valid,
input texels,
input tag,
output ready
);
endinterface

80
hw/rtl/tex/VX_tex_unit.sv
View file

@ -13,15 +13,11 @@ module VX_tex_unit #(
VX_tex_perf_if.master perf_tex_if,
`endif
// Memory interface
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_tex_req_if.slave tex_req_if,
// Outputs
VX_tex_rsp_if.master tex_rsp_if
VX_tex_bus_if.slave tex_bus_if
);
`UNUSED_SPARAM (INSTANCE_ID)
@ -38,7 +34,7 @@ module VX_tex_unit #(
.clk (clk),
.reset (reset),
.dcr_write_if(dcr_write_if),
.stage (tex_req_if.stage),
.stage (tex_bus_if.req_stage),
.tex_dcrs (tex_dcrs)
);
@ -58,7 +54,7 @@ module VX_tex_unit #(
wire req_ready;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign sel_miplevel[i] = tex_req_if.lod[i][`TEX_LOD_BITS-1:0];
assign sel_miplevel[i] = tex_bus_if.req_lod[i][`TEX_LOD_BITS-1:0];
assign sel_mipoff[i] = tex_dcrs.mipoff[sel_miplevel[i]];
end
@ -68,10 +64,10 @@ module VX_tex_unit #(
) pipe_reg (
.clk (clk),
.reset (reset),
.valid_in (tex_req_if.valid),
.ready_in (tex_req_if.ready),
.data_in ({tex_req_if.mask, tex_dcrs.filter, tex_dcrs.format, tex_dcrs.wraps, tex_dcrs.logdims, tex_dcrs.baseaddr, tex_req_if.coords, sel_miplevel, sel_mipoff, tex_req_if.tag}),
.data_out ({req_mask, req_filter, req_format, req_wraps, req_logdims, req_baseaddr, req_coords, req_miplevel, req_mipoff, req_tag}),
.valid_in (tex_bus_if.req_valid),
.ready_in (tex_bus_if.req_ready),
.data_in ({tex_bus_if.req_mask, tex_dcrs.filter, tex_dcrs.format, tex_dcrs.wraps, tex_dcrs.logdims, tex_dcrs.baseaddr, tex_bus_if.req_coords, sel_miplevel, sel_mipoff, tex_bus_if.req_tag}),
.data_out ({req_mask, req_filter, req_format, req_wraps, req_logdims, req_baseaddr, req_coords, req_miplevel, req_mipoff, req_tag}),
.valid_out (req_valid),
.ready_out (req_ready)
);
@ -201,10 +197,10 @@ module VX_tex_unit #(
.reset (reset),
.valid_in (sampler_rsp_valid),
.ready_in (sampler_rsp_ready),
.data_in ({sampler_rsp_data, sampler_rsp_info}),
.data_out ({tex_rsp_if.texels, tex_rsp_if.tag}),
.valid_out (tex_rsp_if.valid),
.ready_out (tex_rsp_if.ready)
.data_in ({sampler_rsp_data, sampler_rsp_info}),
.data_out ({tex_bus_if.rsp_texels, tex_bus_if.rsp_tag}),
.valid_out (tex_bus_if.rsp_valid),
.ready_out (tex_bus_if.rsp_ready)
);
`ifdef PERF_ENABLE
@ -229,7 +225,7 @@ module VX_tex_unit #(
end
end
wire perf_stall_cycle = tex_req_if.valid & ~tex_req_if.ready;
wire perf_stall_cycle = tex_bus_if.req_valid & ~tex_bus_if.req_ready;
reg [`PERF_CTR_BITS-1:0] perf_mem_reads;
reg [`PERF_CTR_BITS-1:0] perf_mem_latency;
@ -254,18 +250,18 @@ module VX_tex_unit #(
`ifdef DBG_TRACE_TEX
always @(posedge clk) begin
if (tex_req_if.valid && tex_req_if.ready) begin
if (tex_bus_if.req_valid && tex_bus_if.req_ready) begin
`TRACE(1, ("%d: %s-req: mask=%b, stage=%0d, lod=0x%0h, u=",
$time, INSTANCE_ID, tex_req_if.mask, tex_req_if.stage, tex_req_if.lod));
`TRACE_ARRAY1D(1, tex_req_if.coords[0], NUM_LANES);
$time, INSTANCE_ID, tex_bus_if.req_mask, tex_bus_if.req_stage, tex_bus_if.req_lod));
`TRACE_ARRAY1D(1, tex_bus_if.req_coords[0], NUM_LANES);
`TRACE(1, (", v="));
`TRACE_ARRAY1D(1, tex_req_if.coords[1], NUM_LANES);
`TRACE(1, (", tag=0x%0h (#%0d)\n", tex_req_if.tag, tex_req_if.tag[TAG_WIDTH-1 -: `UUID_BITS]));
`TRACE_ARRAY1D(1, tex_bus_if.req_coords[1], NUM_LANES);
`TRACE(1, (", tag=0x%0h (#%0d)\n", tex_bus_if.req_tag, tex_bus_if.req_tag[TAG_WIDTH-1 -: `UUID_BITS]));
end
if (tex_rsp_if.valid && tex_rsp_if.ready) begin
if (tex_bus_if.rsp_valid && tex_bus_if.rsp_ready) begin
`TRACE(1, ("%d: %s-rsp: texels=", $time, INSTANCE_ID));
`TRACE_ARRAY1D(1, tex_rsp_if.texels, NUM_LANES);
`TRACE(1, (", tag=0x%0h (#%0d)\n", tex_rsp_if.tag, tex_rsp_if.tag[TAG_WIDTH-1 -: `UUID_BITS]));
`TRACE_ARRAY1D(1, tex_bus_if.rsp_texels, NUM_LANES);
`TRACE(1, (", tag=0x%0h (#%0d)\n", tex_bus_if.rsp_tag, tex_bus_if.rsp_tag[TAG_WIDTH-1 -: `UUID_BITS]));
end
end
`endif
@ -321,28 +317,23 @@ module VX_tex_unit_top #(
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
VX_tex_req_if #(
VX_tex_bus_if #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (TAG_WIDTH)
) tex_req_if();
) tex_bus_if();
VX_tex_rsp_if #(
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (TAG_WIDTH)
) tex_rsp_if();
assign tex_bus_if.req_valid = tex_req_valid;
assign tex_bus_if.req_mask = tex_req_mask;
assign tex_bus_if.req_coords = tex_req_coords;
assign tex_bus_if.req_lod = tex_req_lod;
assign tex_bus_if.req_stage = tex_req_stage;
assign tex_bus_if.req_tag = tex_req_tag;
assign tex_req_ready = tex_bus_if.req_ready;
assign tex_req_if.valid = tex_req_valid;
assign tex_req_if.mask = tex_req_mask;
assign tex_req_if.coords = tex_req_coords;
assign tex_req_if.lod = tex_req_lod;
assign tex_req_if.stage = tex_req_stage;
assign tex_req_if.tag = tex_req_tag;
assign tex_req_ready = tex_req_if.ready;
assign tex_rsp_valid = tex_rsp_if.valid;
assign tex_rsp_texels = tex_rsp_if.texels;
assign tex_rsp_tag = tex_rsp_if.tag;
assign tex_rsp_if.ready = tex_rsp_ready;
assign tex_rsp_valid = tex_bus_if.rsp_valid;
assign tex_rsp_texels = tex_bus_if.rsp_texels;
assign tex_rsp_tag = tex_bus_if.rsp_tag;
assign tex_bus_if.rsp_ready = tex_rsp_ready;
VX_cache_bus_if #(
.NUM_REQS (TCACHE_NUM_REQS),
@ -374,8 +365,7 @@ module VX_tex_unit_top #(
.perf_tex_if (perf_tex_if),
`endif
.dcr_write_if (dcr_write_if),
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if),
.tex_bus_if (tex_bus_if),
.cache_bus_if (cache_bus_if)
);