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renamed fpu bus interface

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This commit is contained in:
Blaise Tine 2023-06-22 11:19:43 -04:00
parent cf77b7d85c
commit 668487088f
11 changed files with 205 additions and 269 deletions
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30
hw/rtl/VX_cluster.sv
View file

@ -319,25 +319,15 @@ module VX_cluster #(
`ifdef EXT_F_ENABLE
VX_fpu_req_if #(
VX_fpu_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB1_TAG_WIDTH)
) per_socket_fpu_req_if[`NUM_SOCKETS]();
) per_socket_fpu_bus_if[`NUM_SOCKETS]();
VX_fpu_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB1_TAG_WIDTH)
) per_socket_fpu_rsp_if[`NUM_SOCKETS]();
VX_fpu_req_if #(
VX_fpu_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB2_TAG_WIDTH)
) fpu_req_if[`NUM_FPU_UNITS]();
VX_fpu_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB2_TAG_WIDTH)
) fpu_rsp_if[`NUM_FPU_UNITS]();
) fpu_bus_if[`NUM_FPU_UNITS]();
`RESET_RELAY (fpu_arb_reset, reset);
@ -351,10 +341,8 @@ module VX_cluster #(
) fpu_arb (
.clk (clk),
.reset (fpu_arb_reset),
.req_in_if (per_socket_fpu_req_if),
.rsp_in_if (per_socket_fpu_rsp_if),
.req_out_if (fpu_req_if),
.rsp_out_if (fpu_rsp_if)
.bus_in_if (per_socket_fpu_bus_if),
.bus_out_if (fpu_bus_if)
);
// Generate all floating-point units
@ -369,8 +357,7 @@ module VX_cluster #(
) fpu_unit (
.clk (clk),
.reset (fpu_reset),
.fpu_req_if (fpu_req_if[i]),
.fpu_rsp_if (fpu_rsp_if[i])
.fpu_bus_if (fpu_bus_if[i])
);
end
@ -470,8 +457,7 @@ module VX_cluster #(
.icache_bus_if (per_socket_icache_bus_if[i]),
`ifdef EXT_F_ENABLE
.fpu_req_if (per_socket_fpu_req_if[i]),
.fpu_rsp_if (per_socket_fpu_rsp_if[i]),
.fpu_bus_if (per_socket_fpu_bus_if[i]),
`endif
`ifdef EXT_TEX_ENABLE

34
hw/rtl/VX_define.vh
View file

@ -415,24 +415,22 @@
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_FPU_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.op_type= src.op_type; \
assign dst.fmt = src.fmt; \
assign dst.frm = src.frm; \
assign dst.dataa = src.dataa; \
assign dst.datab = src.datab; \
assign dst.datac = src.datac; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_FPU_RSP_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.result= src.result; \
assign dst.fflags= src.fflags; \
assign dst.has_fflags = src.has_fflags; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_FPU_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_type = src.req_type; \
assign dst.req_fmt = src.req_fmt; \
assign dst.req_frm = src.req_frm; \
assign dst.req_dataa = src.req_dataa; \
assign dst.req_datab = src.req_datab; \
assign dst.req_datac = src.req_datac; \
assign dst.req_tag = src.req_tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_result = dst.rsp_result; \
assign src.rsp_fflags = dst.rsp_fflags; \
assign src.rsp_has_fflags = dst.rsp_has_fflags; \
assign src.rsp_tag = dst.rsp_tag; \
assign dst.rsp_ready = src.rsp_ready
`define REDUCE_ADD(dst, src, field, width, count) \
wire [count-1:0][width-1:0] __reduce_add_i_``src``field; \

32
hw/rtl/VX_socket.sv
View file

@ -25,8 +25,7 @@ module VX_socket #(
VX_cache_bus_if.master icache_bus_if,
`ifdef EXT_F_ENABLE
VX_fpu_req_if.master fpu_req_if,
VX_fpu_rsp_if.slave fpu_rsp_if,
VX_fpu_bus_if.master fpu_bus_if,
`endif
`ifdef EXT_TEX_ENABLE
@ -174,25 +173,15 @@ module VX_socket #(
`ifdef EXT_F_ENABLE
VX_fpu_req_if #(
VX_fpu_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_TAG_WIDTH)
) per_core_fpu_req_if[`SOCKET_SIZE]();
) per_core_fpu_bus_if[`SOCKET_SIZE]();
VX_fpu_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_TAG_WIDTH)
) per_core_fpu_rsp_if[`SOCKET_SIZE]();
VX_fpu_req_if #(
VX_fpu_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB1_TAG_WIDTH)
) fpu_req_tmp_if[1]();
VX_fpu_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_ARB1_TAG_WIDTH)
) fpu_rsp_tmp_if[1]();
) fpu_bus_tmp_if[1]();
`RESET_RELAY (fpu_arb_reset, reset);
@ -206,13 +195,11 @@ module VX_socket #(
) fpu_arb (
.clk (clk),
.reset (fpu_arb_reset),
.req_in_if (per_core_fpu_req_if),
.rsp_in_if (per_core_fpu_rsp_if),
.req_out_if (fpu_req_tmp_if),
.rsp_out_if (fpu_rsp_tmp_if)
.bus_in_if (per_core_fpu_bus_if),
.bus_out_if (fpu_bus_tmp_if)
);
`ASSIGN_VX_FPU_REQ_IF (fpu_req_if, fpu_req_tmp_if[0]);
`ASSIGN_VX_FPU_BUS_IF (fpu_bus_if, fpu_bus_tmp_if[0]);
`endif
@ -325,8 +312,7 @@ module VX_socket #(
.icache_bus_if (per_core_icache_bus_if[i]),
`ifdef EXT_F_ENABLE
.fpu_req_if (per_core_fpu_req_if[i]),
.fpu_rsp_if (per_core_fpu_rsp_if[i]),
.fpu_bus_if (per_core_fpu_bus_if[i]),
`endif
`ifdef EXT_TEX_ENABLE

48
hw/rtl/core/VX_core.sv
View file

@ -44,8 +44,7 @@ module VX_core #(
VX_cache_bus_if.master icache_bus_if,
`ifdef EXT_F_ENABLE
VX_fpu_req_if.master fpu_req_if,
VX_fpu_rsp_if.slave fpu_rsp_if,
VX_fpu_bus_if.master fpu_bus_if,
`endif
`ifdef EXT_TEX_ENABLE
@ -203,8 +202,7 @@ module VX_core #(
`ifdef EXT_F_ENABLE
.fpu_agent_if (fpu_agent_if),
.fpu_req_if (fpu_req_if),
.fpu_rsp_if (fpu_rsp_if),
.fpu_bus_if (fpu_bus_if),
.fpu_commit_if (fpu_commit_if),
`endif
@ -514,32 +512,27 @@ module VX_core_top #(
assign icache_rsp_ready = icache_bus_if.rsp_ready;
`ifdef EXT_F_ENABLE
VX_fpu_req_if #(
VX_fpu_bus_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_TAG_WIDTH)
) fpu_req_if();
) fpu_bus_if();
VX_fpu_rsp_if #(
.NUM_LANES (`NUM_THREADS),
.TAG_WIDTH (`FPU_REQ_TAG_WIDTH)
) fpu_rsp_if();
assign fpu_req_valid = fpu_bus_if.req_valid;
assign fpu_req_op_type = fpu_bus_if.req_op_type;
assign fpu_req_fmt = fpu_bus_if.req_fmt;
assign fpu_req_frm = fpu_bus_if.req_frm;
assign fpu_req_dataa = fpu_bus_if.req_dataa;
assign fpu_req_datab = fpu_bus_if.req_datab;
assign fpu_req_datac = fpu_bus_if.req_datac;
assign fpu_req_tag = fpu_bus_if.req_tag;
assign fpu_bus_if.req_ready = fpu_req_ready;
assign fpu_req_valid = fpu_req_if.valid;
assign fpu_req_op_type = fpu_req_if.op_type;
assign fpu_req_fmt = fpu_req_if.fmt;
assign fpu_req_frm = fpu_req_if.frm;
assign fpu_req_dataa = fpu_req_if.dataa;
assign fpu_req_datab = fpu_req_if.datab;
assign fpu_req_datac = fpu_req_if.datac;
assign fpu_req_tag = fpu_req_if.tag;
assign fpu_req_if.ready = fpu_req_ready;
assign fpu_rsp_if.valid = fpu_rsp_valid;
assign fpu_rsp_if.result = fpu_rsp_result;
assign fpu_rsp_if.fflags = fpu_rsp_fflags;
assign fpu_rsp_if.has_fflags = fpu_rsp_has_fflags;
assign fpu_rsp_if.tag = fpu_rsp_tag;
assign fpu_rsp_ready = fpu_rsp_if.ready;
assign fpu_bus_if.rsp_valid = fpu_rsp_valid;
assign fpu_bus_if.rsp_result = fpu_rsp_result;
assign fpu_bus_if.rsp_fflags = fpu_rsp_fflags;
assign fpu_bus_if.rsp_has_fflags = fpu_rsp_has_fflags;
assign fpu_bus_if.rsp_tag = fpu_rsp_tag;
assign fpu_rsp_ready = fpu_bus_if.rsp_ready;
`endif
`ifdef EXT_TEX_ENABLE
@ -615,8 +608,7 @@ module VX_core_top #(
.icache_bus_if (icache_bus_if),
`ifdef EXT_F_ENABLE
.fpu_req_if (fpu_req_if),
.fpu_rsp_if (fpu_rsp_if),
.fpu_bus_if (fpu_bus_if),
`endif
`ifdef EXT_TEX_ENABLE

6
hw/rtl/core/VX_execute.sv
View file

@ -31,8 +31,7 @@ module VX_execute #(
`ifdef EXT_F_ENABLE
VX_fpu_agent_if.slave fpu_agent_if,
VX_fpu_req_if.master fpu_req_if,
VX_fpu_rsp_if.slave fpu_rsp_if,
VX_fpu_bus_if.master fpu_bus_if,
VX_commit_if.master fpu_commit_if,
`endif
@ -195,8 +194,7 @@ module VX_execute #(
.clk (clk),
.reset (fpu_reset),
.fpu_agent_if (fpu_agent_if),
.fpu_req_if (fpu_req_if),
.fpu_rsp_if (fpu_rsp_if),
.fpu_bus_if (fpu_bus_if),
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_commit_if (fpu_commit_if),
.csr_pending (csr_pending),

31
hw/rtl/fpu/VX_fpu_agent.sv
View file

@ -15,8 +15,7 @@ module VX_fpu_agent #(
VX_fpu_to_csr_if.master fpu_to_csr_if,
VX_commit_if.master fpu_commit_if,
VX_fpu_req_if.master fpu_req_if,
VX_fpu_rsp_if.slave fpu_rsp_if,
VX_fpu_bus_if.master fpu_bus_if,
input wire csr_pending,
output wire req_pending
@ -38,9 +37,9 @@ module VX_fpu_agent #(
wire mdata_full;
wire fpu_agent_fire = fpu_agent_if.valid && fpu_agent_if.ready;
wire fpu_rsp_fire = fpu_rsp_if.valid && fpu_rsp_if.ready;
wire fpu_rsp_fire = fpu_bus_if.rsp_valid && fpu_bus_if.rsp_ready;
assign rsp_tag = fpu_rsp_if.tag;
assign rsp_tag = fpu_bus_if.rsp_tag;
VX_index_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + `XLEN + `NR_BITS),
@ -82,9 +81,9 @@ module VX_fpu_agent #(
.valid_in (valid_in),
.ready_in (ready_in),
.data_in ({fpu_agent_if.op_type, fpu_agent_if.fmt, req_op_frm, fpu_agent_if.rs1_data, fpu_agent_if.rs2_data, fpu_agent_if.rs3_data, req_tag}),
.data_out ({fpu_req_if.op_type, fpu_req_if.fmt, fpu_req_if.frm, fpu_req_if.dataa, fpu_req_if.datab, fpu_req_if.datac, fpu_req_if.tag}),
.valid_out (fpu_req_if.valid),
.ready_out (fpu_req_if.ready)
.data_out ({fpu_bus_if.req_type, fpu_bus_if.req_fmt, fpu_bus_if.req_frm, fpu_bus_if.req_dataa, fpu_bus_if.req_datab, fpu_bus_if.req_datac, fpu_bus_if.req_tag}),
.valid_out (fpu_bus_if.req_valid),
.ready_out (fpu_bus_if.req_ready)
);
// handle FPU response
@ -94,16 +93,16 @@ module VX_fpu_agent #(
rsp_fflags = '0;
for (integer i = 0; i < `NUM_THREADS; ++i) begin
if (rsp_tmask[i]) begin
rsp_fflags.NX |= fpu_rsp_if.fflags[i].NX;
rsp_fflags.UF |= fpu_rsp_if.fflags[i].UF;
rsp_fflags.OF |= fpu_rsp_if.fflags[i].OF;
rsp_fflags.DZ |= fpu_rsp_if.fflags[i].DZ;
rsp_fflags.NV |= fpu_rsp_if.fflags[i].NV;
rsp_fflags.NX |= fpu_bus_if.rsp_fflags[i].NX;
rsp_fflags.UF |= fpu_bus_if.rsp_fflags[i].UF;
rsp_fflags.OF |= fpu_bus_if.rsp_fflags[i].OF;
rsp_fflags.DZ |= fpu_bus_if.rsp_fflags[i].DZ;
rsp_fflags.NV |= fpu_bus_if.rsp_fflags[i].NV;
end
end
end
assign fpu_to_csr_if.write_enable = fpu_rsp_fire && fpu_rsp_if.has_fflags;
assign fpu_to_csr_if.write_enable = fpu_rsp_fire && fpu_bus_if.rsp_has_fflags;
assign fpu_to_csr_if.write_wid = rsp_wid;
assign fpu_to_csr_if.write_fflags = rsp_fflags;
@ -114,9 +113,9 @@ module VX_fpu_agent #(
) rsp_sbuf (
.clk (clk),
.reset (reset),
.valid_in (fpu_rsp_if.valid),
.ready_in (fpu_rsp_if.ready),
.data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, fpu_rsp_if.result}),
.valid_in (fpu_bus_if.rsp_valid),
.ready_in (fpu_bus_if.rsp_ready),
.data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, fpu_bus_if.rsp_result}),
.data_out ({fpu_commit_if.uuid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.data}),
.valid_out (fpu_commit_if.valid),
.ready_out (fpu_commit_if.ready)

51
hw/rtl/fpu/VX_fpu_arb.sv
View file

@ -13,17 +13,8 @@ module VX_fpu_arb #(
input wire clk,
input wire reset,
// input requests
VX_fpu_req_if.slave req_in_if [NUM_INPUTS],
// input responses
VX_fpu_rsp_if.master rsp_in_if [NUM_INPUTS],
// output request
VX_fpu_req_if.master req_out_if [NUM_OUTPUTS],
// output response
VX_fpu_rsp_if.slave rsp_out_if [NUM_OUTPUTS]
VX_fpu_bus_if.slave bus_in_if [NUM_INPUTS],
VX_fpu_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS);
@ -44,8 +35,8 @@ module VX_fpu_arb #(
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign req_valid_in[i] = req_in_if[i].valid;
assign req_in_if[i].ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign bus_in_if[i].req_ready = req_ready_in[i];
if (NUM_INPUTS > NUM_OUTPUTS) begin
wire [TAG_OUT_WIDTH-1:0] req_tag_in;
@ -55,13 +46,13 @@ module VX_fpu_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_insert (
.data_in (req_in_if[i].tag),
.data_in (bus_in_if[i].req_tag),
.sel_in (LOG_NUM_REQS'(r)),
.data_out (req_tag_in)
);
assign req_data_in[i] = {req_tag_in, req_in_if[i].op_type, req_in_if[i].fmt, req_in_if[i].frm, req_in_if[i].dataa, req_in_if[i].datab, req_in_if[i].datac};
assign req_data_in[i] = {req_tag_in, bus_in_if[i].req_type, bus_in_if[i].req_fmt, bus_in_if[i].req_frm, bus_in_if[i].req_dataa, bus_in_if[i].req_datab, bus_in_if[i].req_datac};
end else begin
assign req_data_in[i] = {req_in_if[i].tag, req_in_if[i].op_type, req_in_if[i].fmt, req_in_if[i].frm, req_in_if[i].dataa, req_in_if[i].datab, req_in_if[i].datac};
assign req_data_in[i] = {bus_in_if[i].req_tag, bus_in_if[i].req_type, bus_in_if[i].req_fmt, bus_in_if[i].req_frm, bus_in_if[i].req_dataa, bus_in_if[i].req_datab, bus_in_if[i].req_datac};
end
end
@ -84,9 +75,9 @@ module VX_fpu_arb #(
);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign req_out_if[i].valid = req_valid_out[i];
assign {req_out_if[i].tag, req_out_if[i].op_type, req_out_if[i].fmt, req_out_if[i].frm, req_out_if[i].dataa, req_out_if[i].datab, req_out_if[i].datac} = req_data_out[i];
assign req_ready_out[i] = req_out_if[i].ready;
assign bus_out_if[i].req_valid = req_valid_out[i];
assign {bus_out_if[i].req_tag, bus_out_if[i].req_type, bus_out_if[i].req_fmt, bus_out_if[i].req_frm, bus_out_if[i].req_dataa, bus_out_if[i].req_datab, bus_out_if[i].req_datac} = req_data_out[i];
assign req_ready_out[i] = bus_out_if[i].req_ready;
end
///////////////////////////////////////////////////////////////////////////
@ -111,16 +102,16 @@ module VX_fpu_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_remove (
.data_in (rsp_out_if[i].tag),
.data_in (bus_out_if[i].rsp_tag),
.data_out (rsp_tag_out)
);
assign rsp_valid_in[i] = rsp_out_if[i].valid;
assign rsp_data_in[i] = {rsp_tag_out, rsp_out_if[i].result, rsp_out_if[i].fflags, rsp_out_if[i].has_fflags};
assign rsp_out_if[i].ready = rsp_ready_in[i];
assign rsp_valid_in[i] = bus_out_if[i].rsp_valid;
assign rsp_data_in[i] = {rsp_tag_out, bus_out_if[i].rsp_result, bus_out_if[i].rsp_fflags, bus_out_if[i].rsp_has_fflags};
assign bus_out_if[i].rsp_ready = rsp_ready_in[i];
if (NUM_INPUTS > 1) begin
assign rsp_sel_in[i] = rsp_out_if[i].tag[TAG_SEL_IDX +: LOG_NUM_REQS];
assign rsp_sel_in[i] = bus_out_if[i].rsp_tag[TAG_SEL_IDX +: LOG_NUM_REQS];
end else begin
assign rsp_sel_in[i] = '0;
end
@ -147,9 +138,9 @@ module VX_fpu_arb #(
end else begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign rsp_valid_in[i] = rsp_out_if[i].valid;
assign rsp_data_in[i] = {rsp_out_if[i].tag, rsp_out_if[i].result, rsp_out_if[i].fflags, rsp_out_if[i].has_fflags};
assign rsp_out_if[i].ready = rsp_ready_in[i];
assign rsp_valid_in[i] = bus_out_if[i].rsp_valid;
assign rsp_data_in[i] = {bus_out_if[i].rsp_tag, bus_out_if[i].rsp_result, bus_out_if[i].rsp_fflags, bus_out_if[i].rsp_has_fflags};
assign bus_out_if[i].rsp_ready = rsp_ready_in[i];
end
VX_stream_arb #(
@ -173,9 +164,9 @@ module VX_fpu_arb #(
end
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign rsp_in_if[i].valid = rsp_valid_out[i];
assign {rsp_in_if[i].tag, rsp_in_if[i].result, rsp_in_if[i].fflags, rsp_in_if[i].has_fflags} = rsp_data_out[i];
assign rsp_ready_out[i] = rsp_in_if[i].ready;
assign bus_in_if[i].rsp_valid = rsp_valid_out[i];
assign {bus_in_if[i].rsp_tag, bus_in_if[i].rsp_result, bus_in_if[i].rsp_fflags, bus_in_if[i].rsp_has_fflags} = rsp_data_out[i];
assign rsp_ready_out[i] = bus_in_if[i].rsp_ready;
end
endmodule

68
hw/rtl/fpu/VX_fpu_bus_if.sv Normal file
View file

@ -0,0 +1,68 @@
`include "VX_define.vh"
`include "VX_fpu_types.vh"
`IGNORE_WARNINGS_BEGIN
import VX_fpu_types::*;
`IGNORE_WARNINGS_END
interface VX_fpu_bus_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire req_valid;
wire [`INST_FPU_BITS-1:0] req_type;
wire [`INST_FMT_BITS-1:0] req_fmt;
wire [`INST_FRM_BITS-1:0] req_frm;
wire [NUM_LANES-1:0][`XLEN-1:0] req_dataa;
wire [NUM_LANES-1:0][`XLEN-1:0] req_datab;
wire [NUM_LANES-1:0][`XLEN-1:0] req_datac;
wire [TAG_WIDTH-1:0] req_tag;
wire req_ready;
wire rsp_valid;
wire [NUM_LANES-1:0][`XLEN-1:0] rsp_result;
fflags_t [NUM_LANES-1:0] rsp_fflags;
wire rsp_has_fflags;
wire [TAG_WIDTH-1:0] rsp_tag;
wire rsp_ready;
modport master (
output req_valid,
output req_type,
output req_fmt,
output req_frm,
output req_dataa,
output req_datab,
output req_datac,
output req_tag,
input req_ready,
input rsp_valid,
input rsp_result,
input rsp_fflags,
input rsp_has_fflags,
input rsp_tag,
output rsp_ready
);
modport slave (
input req_valid,
input req_type,
input req_fmt,
input req_frm,
input req_dataa,
input req_datab,
input req_datac,
input req_tag,
output req_ready,
output rsp_valid,
output rsp_result,
output rsp_fflags,
output rsp_has_fflags,
output rsp_tag,
input rsp_ready
);
endinterface

43
hw/rtl/fpu/VX_fpu_req_if.sv
View file

@ -1,43 +0,0 @@
`include "VX_define.vh"
`include "VX_fpu_types.vh"
interface VX_fpu_req_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`INST_FPU_BITS-1:0] op_type;
wire [`INST_FMT_BITS-1:0] fmt;
wire [`INST_FRM_BITS-1:0] frm;
wire [NUM_LANES-1:0][`XLEN-1:0] dataa;
wire [NUM_LANES-1:0][`XLEN-1:0] datab;
wire [NUM_LANES-1:0][`XLEN-1:0] datac;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output op_type,
output fmt,
output frm,
output dataa,
output datab,
output datac,
output tag,
input ready
);
modport slave (
input valid,
input op_type,
input fmt,
input frm,
input dataa,
input datab,
input datac,
input tag,
output ready
);
endinterface

38
hw/rtl/fpu/VX_fpu_rsp_if.sv
View file

@ -1,38 +0,0 @@
`include "VX_define.vh"
`include "VX_fpu_types.vh"
`IGNORE_WARNINGS_BEGIN
import VX_fpu_types::*;
`IGNORE_WARNINGS_END
interface VX_fpu_rsp_if #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_LANES-1:0][`XLEN-1:0] result;
fflags_t [NUM_LANES-1:0] fflags;
wire has_fflags;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output result,
output fflags,
output has_fflags,
output tag,
input ready
);
modport slave (
input valid,
input result,
input fflags,
input has_fflags,
input tag,
output ready
);
endinterface

93
hw/rtl/fpu/VX_fpu_unit.sv
View file

@ -13,8 +13,7 @@ module VX_fpu_unit #(
input wire clk,
input wire reset,
VX_fpu_req_if.slave fpu_req_if,
VX_fpu_rsp_if.master fpu_rsp_if
VX_fpu_bus_if.slave fpu_bus_if
);
`UNUSED_SPARAM (INSTANCE_ID)
@ -27,22 +26,22 @@ module VX_fpu_unit #(
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.op_type (fpu_req_if.op_type),
.fmt (fpu_req_if.fmt),
.frm (fpu_req_if.frm),
.dataa (fpu_req_if.dataa),
.datab (fpu_req_if.datab),
.datac (fpu_req_if.datac),
.tag_in (fpu_req_if.tag),
.ready_in (fpu_req_if.ready),
.valid_in (fpu_bus_if.req_valid),
.op_type (fpu_bus_if.req_type),
.fmt (fpu_bus_if.req_fmt),
.frm (fpu_bus_if.req_frm),
.dataa (fpu_bus_if.req_dataa),
.datab (fpu_bus_if.req_datab),
.datac (fpu_bus_if.req_datac),
.tag_in (fpu_bus_if.req_tag),
.ready_in (fpu_bus_if.req_ready),
.valid_out (fpu_rsp_if.valid),
.result (fpu_rsp_if.result),
.has_fflags (fpu_rsp_if.has_fflags),
.fflags (fpu_rsp_if.fflags),
.tag_out (fpu_rsp_if.tag),
.ready_out (fpu_rsp_if.ready)
.valid_out (fpu_bus_if.rsp_valid),
.result (fpu_bus_if.rsp_result),
.has_fflags (fpu_bus_if.rsp_has_fflags),
.fflags (fpu_bus_if.rsp_fflags),
.tag_out (fpu_bus_if.rsp_tag),
.ready_out (fpu_bus_if.rsp_ready)
);
`elsif FPU_FPNEW
@ -54,22 +53,22 @@ module VX_fpu_unit #(
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.op_type (fpu_req_if.op_type),
.fmt (fpu_req_if.fmt),
.frm (fpu_req_if.frm),
.dataa (fpu_req_if.dataa),
.datab (fpu_req_if.datab),
.datac (fpu_req_if.datac),
.tag_in (fpu_req_if.tag),
.ready_in (fpu_req_if.ready),
.valid_in (fpu_bus_if.req_valid),
.op_type (fpu_bus_if.req_op_type),
.fmt (fpu_bus_if.req_fmt),
.frm (fpu_bus_if.req_frm),
.dataa (fpu_bus_if.req_dataa),
.datab (fpu_bus_if.req_datab),
.datac (fpu_bus_if.req_datac),
.tag_in (fpu_bus_if.req_tag),
.ready_in (fpu_bus_if.req_ready),
.valid_out (fpu_rsp_if.valid),
.result (fpu_rsp_if.result),
.has_fflags (fpu_rsp_if.has_fflags),
.fflags (fpu_rsp_if.fflags),
.tag_out (fpu_rsp_if.tag),
.ready_out (fpu_rsp_if.ready)
.valid_out (fpu_bus_if.rsp_valid),
.result (fpu_bus_if.rsp_result),
.has_fflags (fpu_bus_if.rsp_has_fflags),
.fflags (fpu_bus_if.rsp_fflags),
.tag_out (fpu_bus_if.rsp_tag),
.ready_out (fpu_bus_if.rsp_ready)
);
`elsif FPU_DSP
@ -81,22 +80,22 @@ module VX_fpu_unit #(
.clk (clk),
.reset (reset),
.valid_in (fpu_req_if.valid),
.op_type (fpu_req_if.op_type),
.fmt (fpu_req_if.fmt),
.frm (fpu_req_if.frm),
.dataa (fpu_req_if.dataa),
.datab (fpu_req_if.datab),
.datac (fpu_req_if.datac),
.tag_in (fpu_req_if.tag),
.ready_in (fpu_req_if.ready),
.valid_in (fpu_bus_if.req_valid),
.op_type (fpu_bus_if.req_op_type),
.fmt (fpu_bus_if.req_fmt),
.frm (fpu_bus_if.req_frm),
.dataa (fpu_bus_if.req_dataa),
.datab (fpu_bus_if.req_datab),
.datac (fpu_bus_if.req_datac),
.tag_in (fpu_bus_if.req_tag),
.ready_in (fpu_bus_if.req_ready),
.valid_out (fpu_rsp_if.valid),
.result (fpu_rsp_if.result),
.has_fflags (fpu_rsp_if.has_fflags),
.fflags (fpu_rsp_if.fflags),
.tag_out (fpu_rsp_if.tag),
.ready_out (fpu_rsp_if.ready)
.valid_out (fpu_bus_if.rsp_valid),
.result (fpu_bus_if.rsp_result),
.has_fflags (fpu_bus_if.rsp_has_fflags),
.fflags (fpu_bus_if.rsp_fflags),
.tag_out (fpu_bus_if.rsp_tag),
.ready_out (fpu_bus_if.rsp_ready)
);
`endif