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minor update

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This commit is contained in:
Blaise Tine 2024-07-14 03:12:30 -07:00
parent f0ebe94253
commit 0dbcddcb54
4 changed files with 102 additions and 38 deletions
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51
sim/opaesim/opae_sim.cpp
View file

@ -269,20 +269,8 @@ public:
private:
void reset() {
cci_reads_.clear();
cci_writes_.clear();
device_->vcp2af_sRxPort_c0_mmioRdValid = 0;
device_->vcp2af_sRxPort_c0_mmioWrValid = 0;
device_->vcp2af_sRxPort_c0_rspValid = 0;
device_->vcp2af_sRxPort_c1_rspValid = 0;
device_->vcp2af_sRxPort_c0_TxAlmFull = 0;
device_->vcp2af_sRxPort_c1_TxAlmFull = 0;
for (int b = 0; b < MEMORY_BANKS; ++b) {
pending_mem_reqs_[b].clear();
device_->avs_readdatavalid[b] = 0;
device_->avs_waitrequest[b] = 0;
}
this->cci_bus_reset();
this->avs_bus_reset();
device_->reset = 1;
@ -307,9 +295,8 @@ private:
}
void tick() {
this->sRxPort_bus();
this->sTxPort_bus();
this->avs_bus();
this->cci_bus_eval();
this->avs_bus_eval();
if (!dram_queue_.empty()) {
if (ramulator_->send(dram_queue_.front()))
@ -345,7 +332,23 @@ private:
++timestamp;
}
void sRxPort_bus() {
void cci_bus_reset() {
cci_reads_.clear();
cci_writes_.clear();
device_->vcp2af_sRxPort_c0_mmioRdValid = 0;
device_->vcp2af_sRxPort_c0_mmioWrValid = 0;
device_->vcp2af_sRxPort_c0_rspValid = 0;
device_->vcp2af_sRxPort_c1_rspValid = 0;
device_->vcp2af_sRxPort_c0_TxAlmFull = 0;
device_->vcp2af_sRxPort_c1_TxAlmFull = 0;
}
void cci_bus_eval() {
this->sRxPort_bus_eval();
this->sTxPort_bus_eval();
}
void sRxPort_bus_eval() {
// check mmio request
bool mmio_req_enabled = device_->vcp2af_sRxPort_c0_mmioRdValid
|| device_->vcp2af_sRxPort_c0_mmioWrValid;
@ -395,7 +398,7 @@ private:
}
}
void sTxPort_bus() {
void sTxPort_bus_eval() {
// process read requests
if (device_->af2cp_sTxPort_c0_valid) {
assert(!device_->vcp2af_sRxPort_c0_TxAlmFull);
@ -425,7 +428,15 @@ private:
device_->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= (CCI_WQ_SIZE-1));
}
void avs_bus() {
void avs_bus_reset() {
for (int b = 0; b < MEMORY_BANKS; ++b) {
pending_mem_reqs_[b].clear();
device_->avs_readdatavalid[b] = 0;
device_->avs_waitrequest[b] = 0;
}
}
void avs_bus_eval() {
for (int b = 0; b < MEMORY_BANKS; ++b) {
// process memory responses
device_->avs_readdatavalid[b] = 0;

30
sim/rtlsim/processor.cpp
View file

@ -241,12 +241,12 @@ private:
mem_wr_rsp_active_ = false;
#ifdef AXI_BUS
this->reset_axi_bus();
this->axi_bus_reset();
#else
this->reset_avs_bus();
this->avs_bus_reset();
#endif
this->reset_dcr_bus();
this->dcr_bus_reset();
device_->reset = 1;
@ -264,21 +264,21 @@ private:
this->eval();
#ifdef AXI_BUS
this->eval_axi_bus(0);
this->axi_bus_eval(0);
#else
this->eval_avs_bus(0);
this->avs_bus_eval(0);
#endif
this->eval_dcr_bus(0);
this->dcr_bus_eval(0);
device_->clk = 1;
this->eval();
#ifdef AXI_BUS
this->eval_axi_bus(1);
this->axi_bus_eval(1);
#else
this->eval_avs_bus(1);
this->avs_bus_eval(1);
#endif
this->eval_dcr_bus(1);
this->dcr_bus_eval(1);
if (MEM_CYCLE_RATIO > 0) {
auto cycle = timestamp / 2;
@ -313,7 +313,7 @@ private:
#ifdef AXI_BUS
void reset_axi_bus() {
void axi_bus_reset() {
device_->m_axi_wready[0] = 0;
device_->m_axi_awready[0] = 0;
device_->m_axi_arready[0] = 0;
@ -321,7 +321,7 @@ private:
device_->m_axi_bvalid[0] = 0;
}
void eval_axi_bus(bool clk) {
void axi_bus_eval(bool clk) {
if (!clk) {
mem_rd_rsp_ready_ = device_->m_axi_rready[0];
mem_wr_rsp_ready_ = device_->m_axi_bready[0];
@ -474,12 +474,12 @@ private:
#else
void reset_avs_bus() {
void avs_bus_reset() {
device_->mem_req_ready = 0;
device_->mem_rsp_valid = 0;
}
void eval_avs_bus(bool clk) {
void avs_bus_eval(bool clk) {
if (!clk) {
mem_rd_rsp_ready_ = device_->mem_rsp_ready;
return;
@ -592,11 +592,11 @@ private:
#endif
void reset_dcr_bus() {
void dcr_bus_reset() {
device_->dcr_wr_valid = 0;
}
void eval_dcr_bus(bool clk) {
void dcr_bus_eval(bool clk) {
if (!clk) {
return;
}

1
sim/xrtsim/vortex_afu_shim.sv
View file

@ -50,7 +50,6 @@ module vortex_afu_shim #(
output wire interrupt
`IGNORE_WARNINGS_END
);
vortex_afu #(
.C_S_AXI_CTRL_ADDR_WIDTH(C_S_AXI_CTRL_ADDR_WIDTH),
.C_S_AXI_CTRL_DATA_WIDTH(C_S_AXI_CTRL_DATA_WIDTH),

58
sim/xrtsim/xrt_sim.cpp
View file

@ -192,7 +192,8 @@ public:
private:
void reset() {
//--
this->axi_ctrl_bus_reset();
this->axi_mem_bus_reset();
device_->ap_rst_n = 0;
@ -217,7 +218,8 @@ private:
}
void tick() {
//--
this->axi_ctrl_bus_eval();
this->axi_mem_bus_eval();
if (!dram_queue_.empty()) {
if (ramulator_->send(dram_queue_.front()))
@ -253,6 +255,58 @@ private:
++timestamp;
}
void axi_ctrl_bus_reset() {
// address write request
device_->s_axi_ctrl_awvalid = 0;
//device_->s_axi_ctrl_awaddr = 0;
// data write request
device_->s_axi_ctrl_wvalid = 0;
//device_->s_axi_ctrl_wdata = 0;
//device_->s_axi_ctrl_wstrb = 0;
// address read request
device_->s_axi_ctrl_arvalid = 0;
//device_->s_axi_ctrl_araddr = 0;
// data read response
device_->s_axi_ctrl_rready = 0;
// data write response
device_->s_axi_ctrl_bready = 0;
}
void axi_ctrl_bus_eval() {
//--
}
void axi_mem_bus_reset() {
// address write request
device_->m_axi_mem_0_awready = 0;
// data write request
device_->m_axi_mem_0_wready = 0;
// address read request
device_->m_axi_mem_0_arready = 0;
// data read response
device_->m_axi_mem_0_rvalid = 0;
//device_->m_axi_mem_0_rdata = 0;
//device_->m_axi_mem_0_rlast = 0;
//device_->m_axi_mem_0_rid = 0;
//device_->m_axi_mem_0_rresp = 0;
// data write response
device_->m_axi_mem_0_bvalid = 0;
//device_->m_axi_mem_0_bresp = 0;
//device_->m_axi_mem_0_bid = 0;
}
void axi_mem_bus_eval() {
//--
}
Vvortex_afu_shim *device_;
RAM* ram_;
ramulator::Gem5Wrapper* ramulator_;