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migrated 100% to modelsim

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This commit is contained in:
felsabbagh3 2019-10-27 20:08:44 -04:00
parent 715982cca7
commit 0ee74bc566
13 changed files with 282 additions and 157 deletions
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2
.gitignore vendored
View file

@ -1,4 +1,6 @@
./rtl/obj_dir/
./rtl/obj_dir/*.vcd
./rtl/.*
./rtl/modelsim/*.vcd
*.vcd
.*

18
kernel/vortex_test.dump
View file

@ -1660,14 +1660,16 @@ Disassembly of section .text:
80001848: 00112623 sw ra,12(sp)
8000184c: 00812423 sw s0,8(sp)
80001850: 01010413 addi s0,sp,16
80001854: 00b00513 li a0,11
80001858: fa5fe0ef jal ra,800007fc <vx_print_hex>
8000185c: 00000793 li a5,0
80001860: 00078513 mv a0,a5
80001864: 00c12083 lw ra,12(sp)
80001868: 00812403 lw s0,8(sp)
8000186c: 01010113 addi sp,sp,16
80001870: 00008067 ret
80001854: ed5ff0ef jal ra,80001728 <initialize_mats>
80001858: 810267b7 lui a5,0x81026
8000185c: 22078513 addi a0,a5,544 # 81026220 <barrier_bool+0xffffcf58>
80001860: f3dff0ef jal ra,8000179c <print_matrix>
80001864: 00000793 li a5,0
80001868: 00078513 mv a0,a5
8000186c: 00c12083 lw ra,12(sp)
80001870: 00812403 lw s0,8(sp)
80001874: 01010113 addi sp,sp,16
80001878: 00008067 ret
Disassembly of section .rodata:

BIN
kernel/vortex_test.elf
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Binary file not shown.

6
kernel/vortex_test.hex
View file

@ -388,9 +388,9 @@
:10182000E3D2E7FAB707008113854714EFE05FF9C9
:10183000130000008320C10203248102130101036D
:1018400067800000130101FF23261100232481007B
:10185000130401011305B000EFE05FFA93070000E5
:10186000138507008320C1000324810013010101B7
:04187000678000008D
:1018500013040101EFF05FEDB767028113850722E2
:10186000EFF0DFF393070000138507008320C1002A
:0C187000032481001301010167800000C7
:02000004810079
:10000000300000003100000032000000330000002A
:10001000340000003500000036000000370000000A

8
kernel/vx_main.c
View file

@ -43,17 +43,17 @@ int main()
// unsigned f = temp;
vx_print_hex(11);
// vx_printc(0, 'a');
// vx_print_hex(11);
// vx_printc(0, 'k');
// initialize_mats();
initialize_mats();
// matrix multiplication
// vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z);
// print_matrix(x);
print_matrix(x);
// // matrix addition
// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);

16
kernel/vx_os/vx_back/vx_back.s
View file

@ -10,22 +10,22 @@ _start:
# li a1, 7
# sw a1, 0(a0)
# la a0, 0x10000048
# li a1, 3
# sw a1, 0(a0)
# # la a0, 0x10000048
# # li a1, 3
# # sw a1, 0(a0)
# la a0, 0x80000000
# li a1, 9
# sw a1, 0(a0)
# la a0, 0x80000008
# li a1, 8
# sw a1, 0(a0)
# # la a0, 0x80000008
# # li a1, 8
# # sw a1, 0(a0)
# la a0, 0x10000000
# lw a2, 0(a0)
# la a0, 0x10000048
# lw a3, 0(a0)
# # la a0, 0x10000048
# # lw a3, 0(a0)
# # la a0, 0x00000000 # I=0,OF=0, B=0
# # li a1, 1
# # sw a1, 0(a0)

7
rtl/Vortex.v
View file

@ -7,7 +7,9 @@ module Vortex
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
parameter CACHE_BANKS = 8,
localparam NUMBER_BANKS = 8,
localparam NUM_WORDS_PER_BLOCK = 4
)
(
input wire clk,
@ -30,9 +32,6 @@ module Vortex
output wire out_ebreak
);
localparam NUMBER_BANKS = 8;
localparam NUM_WORDS_PER_BLOCK = 4;
wire memory_delay;
wire gpr_stage_delay;
wire schedule_delay;

8
rtl/modelsim/Makefile
View file

@ -4,6 +4,7 @@ ALL:sim
#TOOL INPUT
SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../VX_define.v \
../interfaces/VX_branch_response_inter.v \
@ -72,13 +73,13 @@ SRC = \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v \
vortex_dpi.cpp
../shared_memory/VX_shared_memory_block.v
# vortex_dpi.h
CMD= \
-do "vcd file vortex.vcd; \
vcd add -r /vortex/*; \
vcd add -r /vortex_tb/*; \
run -all; \
quit -f"
@ -95,6 +96,7 @@ LOG=
comp:
vlog -O0 $(OPT) -work $(LIB) $(SRC)
# vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC)
sim: comp

250
rtl/modelsim/vortex_dpi.cpp
View file

@ -10,15 +10,22 @@
#include "../simulate/VX_define.h"
// #include "vortex_dpi.h"
extern "C" {
void load_file(char * filename);
void ibus_driver(int pc_addr, int * instruction);
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready);
void io_handler(bool io_valid, int io_data);
void load_file (char * filename);
void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
}
RAM ram;
bool refill;
unsigned refill_addr;
unsigned getIndex(int, int, int);
unsigned getIndex(int r, int c, int numCols)
{
return (r * numCols) + c;
@ -27,119 +34,174 @@ unsigned getIndex(int r, int c, int numCols)
void load_file(char * filename)
{
printf("\n\n\n\n**********************\n");
// printf("\n\n\n\n**********************\n");
// printf("Inside load_file\n");
fprintf(stderr, "\n\n\n\n**********************\n");
loadHexImpl(filename, &ram);
// printf("Filename: %s\n", filename);
refill = false;
}
void ibus_driver(int pc_addr, int * instruction)
void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction)
{
// printf("Inside ibus_driver\n");
uint32_t curr_inst = 0;
curr_inst = 0xdeadbeef;
uint32_t u_pc_addr = (uint32_t) (pc_addr);
ram.getWord(u_pc_addr, &curr_inst);
// printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction);
(*instruction) = curr_inst;
}
bool refill;
unsigned refill_addr;
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready)
{
// printf("Inside dbus_driver\n");
(*i_m_ready )= 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
if (clk)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
i_m_readdata[getIndex(i,j, CACHE_WORDS_PER_BLOCK)] = 0;
}
}
if (refill)
{
refill = false;
*i_m_ready = 1;
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value;
ram.getWord(new_addr, &value);
// printf("-------- (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
i_m_readdata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)] = value;
}
(*instruction) = 0;
}
else
{
if (o_m_valid)
uint32_t curr_inst = 0;
curr_inst = 0xdeadbeef;
uint32_t u_pc_addr = (uint32_t) (pc_addr);
ram.getWord(u_pc_addr, &curr_inst);
// printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction);
(*instruction) = curr_inst;
}
}
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
// printf("Valid o_m_valid\n");
if (o_m_read_or_write)
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
// printf("Valid write\n");
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned index = getIndex(i,j, CACHE_WORDS_PER_BLOCK);
real_i_m_readdata[index].aval = 0x506070;
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)];
ram.writeWord( new_addr, &new_value);
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
}
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, CACHE_WORDS_PER_BLOCK)] = 0;
}
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
if (clk)
{
// Do nothing on positive edge
}
else
{
if (refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value;
ram.getWord(new_addr, &value);
// fprintf(stderr, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK)];
ram.writeWord( new_addr, &new_value);
// fprintf(stderr, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
}
}
}
}
void io_handler(bool clk, bool io_valid, unsigned io_data)
{
// printf("Inside io_handler\n");
if (clk)
{
// Do nothing
}
else
{
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
char c = (char) data_write;
fprintf(stderr, "%c", c );
fflush(stderr);
}
}
}
void io_handler(bool io_valid, int io_data)
void gracefulExit()
{
// printf("Inside io_handler\n");
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
char c = (char) data_write;
printf("%c", c);
printf("YOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYO\n");
fflush(stdout);
}
fprintf(stderr, "\n*********************\n\n");
}

8
rtl/modelsim/vortex_dpi.h Normal file
View file

@ -0,0 +1,8 @@
extern "C" {
void load_file (char * filename);
void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svOpenArrayHandle * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
}

57
rtl/modelsim/vortex_tb.v
View file

@ -8,26 +8,31 @@
import "DPI-C" load_file = function void load_file(input string filename);
import "DPI-C" ibus_driver = function void ibus_driver(input int pc_addr,
import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
output int instruction);
import "DPI-C" dbus_driver = function void dbus_driver( input int o_m_read_addr,
import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input reg o_m_valid,
input reg [31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
input reg o_m_read_or_write,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
// Rsp
output reg [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
output reg i_m_ready);
output reg[31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" io_handler = function void io_handler(input reg io_valid, input int io_data);
import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
import "DPI-C" gracefulExit = function void gracefulExit();
module vortex_tb (
);
reg[31:0] cycle_num;
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
@ -43,15 +48,14 @@ module vortex_tb (
reg o_m_read_or_write;
// Rsp
reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
reg i_m_ready;
reg out_ebreak;
reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
reg i_m_ready;
reg out_ebreak;
reg[31:0] hi;
integer temp;
integer num_cycles;
initial begin
// $fdumpfile("vortex1.vcd");
@ -61,7 +65,7 @@ module vortex_tb (
clk = 0;
#5 reset = 1;
clk = 1;
num_cycles = 0;
cycle_num = 0;
end
Vortex vortex(
@ -81,31 +85,26 @@ module vortex_tb (
.out_ebreak (out_ebreak)
);
always @(*) begin
ibus_driver(clk, icache_request_pc_address, icache_response_instruction);
dbus_driver(clk, o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
io_handler (clk, io_valid, io_data);
end
always @(clk, posedge reset) begin
// $display("FROM ALWAYS");
// $display("num_cycles: %d",num_cycles);
num_cycles = num_cycles + 1;
if (num_cycles == 1000) begin
// $dumpall;
// $dumpflush;
// $finish;
end
// if (num_cycles == 1000) $stop;
if (reset) begin
reset = 0;
clk = 0;
end
if (clk == 0) begin
ibus_driver(icache_request_pc_address, icache_response_instruction);
dbus_driver(o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
io_handler(io_valid, io_data);
#5 clk <= ~clk;
if (out_ebreak) begin
gracefulExit();
$finish;
end
// $display("clk: %d, out_ebreak: %d",clk, out_ebreak);
#5 clk <= ~clk;
if (out_ebreak) $finish;
end
endmodule

14
rtl/simulate/ram.h
View file

@ -9,6 +9,12 @@
// #define NULL 0
class RAM;
uint32_t hti(char);
uint32_t hToI(char *, uint32_t);
void loadHexImpl(char *,RAM*);
class RAM{
public:
uint8_t* mem[1 << 12];
@ -36,10 +42,10 @@ public:
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0xFF;
ptr[i + 1] = 0xFF;
ptr[i + 2] = 0xFF;
ptr[i + 3] = 0xFF;
ptr[i + 0] = 0x00;
ptr[i + 1] = 0x00;
ptr[i + 2] = 0x00;
ptr[i + 3] = 0x00;
}
mem[address >> 20] = ptr;
}

45
sftp-config.json Normal file
View file

@ -0,0 +1,45 @@
{
// The tab key will cycle through the settings when first created
// Visit http://wbond.net/sublime_packages/sftp/settings for help
// sftp, ftp or ftps
"type": "sftp",
"save_before_upload": true,
"upload_on_save": true,
"sync_down_on_open": false,
"sync_skip_deletes": false,
"sync_same_age": true,
"confirm_downloads": false,
"confirm_sync": true,
"confirm_overwrite_newer": false,
"host": "ece-rschsrv01.ece.gatech.edu",
"user": "felsabbagh3",
//"password": "password",
//"port": "22",
"remote_path": "/nethome/felsabbagh3/research/Vortex/",
"ignore_regexes": [
"\\.sublime-(project|workspace)", "sftp-config(-alt\\d?)?\\.json",
"sftp-settings\\.json", "/venv/", "\\.svn/", "\\.hg/", "\\.git/",
"\\.bzr", "_darcs", "CVS", "\\.DS_Store", "Thumbs\\.db", "desktop\\.ini"
],
//"file_permissions": "664",
//"dir_permissions": "775",
//"extra_list_connections": 0,
"connect_timeout": 30,
//"keepalive": 120,
//"ftp_passive_mode": true,
//"ftp_obey_passive_host": false,
//"ssh_key_file": "~/.ssh/id_rsa",
//"sftp_flags": ["-F", "/path/to/ssh_config"],
//"preserve_modification_times": false,
//"remote_time_offset_in_hours": 0,
//"remote_encoding": "utf-8",
//"remote_locale": "C",
//"allow_config_upload": false,
}