mirror of
https://github.com/vortexgpgpu/vortex.git
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Modelsim Working + Simulating + dumping - Some bugs
This commit is contained in:
felsabbagh3
parent
372c81d90c
commit
715982cca7
24 changed files with 374 additions and 142 deletions
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@ -1660,16 +1660,14 @@ Disassembly of section .text:
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80001848: 00112623 sw ra,12(sp)
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8000184c: 00812423 sw s0,8(sp)
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80001850: 01010413 addi s0,sp,16
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80001854: ed5ff0ef jal ra,80001728 <initialize_mats>
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80001858: 810267b7 lui a5,0x81026
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8000185c: 22078513 addi a0,a5,544 # 81026220 <barrier_bool+0xffffcf58>
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80001860: f3dff0ef jal ra,8000179c <print_matrix>
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80001864: 00000793 li a5,0
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80001868: 00078513 mv a0,a5
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8000186c: 00c12083 lw ra,12(sp)
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80001870: 00812403 lw s0,8(sp)
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80001874: 01010113 addi sp,sp,16
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80001878: 00008067 ret
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80001854: 00b00513 li a0,11
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80001858: fa5fe0ef jal ra,800007fc <vx_print_hex>
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8000185c: 00000793 li a5,0
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80001860: 00078513 mv a0,a5
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80001864: 00c12083 lw ra,12(sp)
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80001868: 00812403 lw s0,8(sp)
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8000186c: 01010113 addi sp,sp,16
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80001870: 00008067 ret
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Disassembly of section .rodata:
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Binary file not shown.
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@ -388,9 +388,9 @@
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:10182000E3D2E7FAB707008113854714EFE05FF9C9
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:10183000130000008320C10203248102130101036D
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:1018400067800000130101FF23261100232481007B
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:1018500013040101EFF05FEDB767028113850722E2
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:10186000EFF0DFF393070000138507008320C1002A
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:0C187000032481001301010167800000C7
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:10185000130401011305B000EFE05FFA93070000E5
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:10186000138507008320C1000324810013010101B7
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:04187000678000008D
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:02000004810079
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:10000000300000003100000032000000330000002A
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:10001000340000003500000036000000370000000A
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@ -43,17 +43,17 @@ int main()
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// unsigned f = temp;
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// vx_print_hex(11);
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vx_print_hex(11);
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// vx_printc(0, 'a');
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initialize_mats();
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// initialize_mats();
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// matrix multiplication
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// vx_sq_mat_mult(x, y, z, MAT_DIM);
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// vx_print_str("\n\nMatrix multiplication\n");
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// print_matrix(z);
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print_matrix(x);
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// print_matrix(x);
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// // matrix addition
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// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);
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@ -1,5 +1,5 @@
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// `include "VX_define.v"
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`include "VX_define.v"
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module VX_decode(
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// Fetch Inputs
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@ -75,7 +75,16 @@ module VX_decode(
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reg[4:0] csr_alu;
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reg[4:0] alu_op;
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reg[4:0] mul_alu;
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reg[19:0] temp_upper_immed;
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reg temp_jal;
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reg[31:0] temp_jal_offset;
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reg[31:0] temp_itype_immed;
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reg[2:0] temp_branch_type;
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reg temp_branch_stall;
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// always @(posedge reset) begin
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// end
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assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid;
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@ -147,7 +156,6 @@ module VX_decode(
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assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
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// UPPER IMMEDIATE
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reg[19:0] temp_upper_immed;
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always @(*) begin
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case(curr_opcode)
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`LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
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@ -179,8 +187,6 @@ module VX_decode(
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assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef;
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// JAL
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reg temp_jal;
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reg[31:0] temp_jal_offset;
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always @(*) begin
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case(curr_opcode)
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`JAL_INST:
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@ -235,7 +241,6 @@ module VX_decode(
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assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
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reg[31:0] temp_itype_immed;
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always @(*) begin
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case(curr_opcode)
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`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
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@ -249,8 +254,7 @@ module VX_decode(
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assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed;
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reg[2:0] temp_branch_type;
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reg temp_branch_stall;
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always @(*) begin
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case(curr_opcode)
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`B_INST:
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@ -1,5 +1,5 @@
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// `include "VX_define.v"
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`include "VX_define.v"
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module VX_dmem_controller (
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input wire clk,
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@ -39,6 +39,7 @@ module VX_dmem_controller (
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VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
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.clk (clk),
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.reset (reset),
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.in_valid (sm_driver_in_valid),
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.in_address(cache_driver_in_address),
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.in_data (cache_driver_in_data),
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@ -80,12 +80,15 @@ module VX_fetch (
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.out_ebreak (out_ebreak)
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);
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// always @(*) begin
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// $display("Inside verilog instr: %h, pc: %h", icache_response.instruction, warp_pc);
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// end
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assign icache_request.pc_address = warp_pc;
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assign fe_inst_meta_fd.warp_num = warp_num;
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assign fe_inst_meta_fd.valid = thread_mask;
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assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction;;
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assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction;
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assign fe_inst_meta_fd.inst_pc = warp_pc;
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@ -3,6 +3,7 @@
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module VX_gpr (
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input wire clk,
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input wire reset,
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input wire valid_write_request,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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@ -23,6 +24,7 @@ module VX_gpr (
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byte_enabled_simple_dual_port_ram first_ram(
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.we (write_enable),
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.clk (clk),
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.reset (reset),
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.waddr (VX_writeback_inter.rd),
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.raddr1(VX_gpr_read.rs1),
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.raddr2(VX_gpr_read.rs2),
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@ -49,7 +49,8 @@ module VX_gpr_stage (
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VX_gpr_wrapper vx_grp_wrapper(
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.VX_writeback_inter(VX_writeback_inter),
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.VX_gpr_read (VX_gpr_read),
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.VX_gpr_jal (VX_gpr_jal),
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@ -2,6 +2,7 @@
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module VX_gpr_wrapper (
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input wire clk,
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input wire reset,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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VX_gpr_jal_inter VX_gpr_jal,
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@ -30,6 +31,7 @@ module VX_gpr_wrapper (
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wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
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VX_gpr vx_gpr(
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.clk (clk),
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.reset (reset),
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.valid_write_request(valid_write_request),
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.VX_gpr_read (VX_gpr_read),
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.VX_writeback_inter (VX_writeback_inter),
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@ -38,7 +38,7 @@ module VX_warp (
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end
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always @(posedge clk) begin
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always @(posedge clk, posedge reset) begin
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if (remove) begin
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valid <= valid_zero;
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end else if (in_change_mask) begin
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@ -109,16 +109,20 @@ module VX_warp_scheduler (
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/* verilator lint_on UNUSED */
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integer curr_w_help;
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integer curr_barrier;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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barrier_stall_mask[0] <= 0;
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barrier_stall_mask[1] <= 0;
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for (curr_barrier = 0; curr_barrier < `NUM_BARRIERS; curr_barrier=curr_barrier+1) begin
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barrier_stall_mask[curr_barrier] <= 0;
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end
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use_wsapwn_pc <= 0;
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use_wsapwn <= 0;
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warp_pcs[0] <= (32'h80000000 - 4);
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warp_active[0] <= 1; // Activating first warp
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visible_active[0] <= 1; // Activating first warp
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thread_masks[0] <= 1; // Activating first thread in first warp
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warp_stalled <= 0;
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total_barrier_stall = 0;
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for (curr_w_help = 1; curr_w_help < `NW; curr_w_help=curr_w_help+1) begin
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warp_pcs[curr_w_help] <= 0;
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warp_active[curr_w_help] <= 0; // Activating first warp
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@ -283,6 +287,10 @@ module VX_warp_scheduler (
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.found (schedule)
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);
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// always @(*) begin
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// $display("WarpPC: %h",warp_pc);
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// $display("real_schedule: %d, schedule: %d, warp_stalled: %d, warp_to_schedule: %d, total_barrier_stall: %d",real_schedule, schedule, warp_stalled[warp_to_schedule], warp_to_schedule, total_barrier_stall[warp_to_schedule]);
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// end
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// Valid counter
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@ -5,6 +5,7 @@
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module byte_enabled_simple_dual_port_ram
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(
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input we, clk,
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input wire reset,
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input wire[4:0] waddr, raddr1, raddr2,
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input wire[`NT_M1:0] be,
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input wire[`NT_M1:0][31:0] wdata,
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@ -17,13 +18,15 @@ module byte_enabled_simple_dual_port_ram
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// Thread Byte Bit
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logic [`NT_M1:0][3:0][7:0] GPR[31:0];
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integer ini;
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initial begin
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for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
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end
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// initial begin
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// for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
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// end
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always@(posedge clk) begin
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if(we) begin
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integer ini;
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always@(posedge clk, posedge reset) begin
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if (reset) begin
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for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
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end else if(we) begin
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integer thread_ind;
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for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin
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if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
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3
rtl/cache/VX_Cache_Bank.v
vendored
3
rtl/cache/VX_Cache_Bank.v
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@ -15,6 +15,7 @@ module VX_Cache_Bank
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)
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(
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clk,
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rst,
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state,
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read_or_write, // Read = 0 | Write = 1
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i_p_mem_read,
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@ -49,6 +50,7 @@ module VX_Cache_Bank
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localparam RECIV_MEM_RSP = 2;
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// Inputs
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input wire rst;
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input wire clk;
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input wire [3:0] state;
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//input wire write_from_mem;
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@ -175,6 +177,7 @@ module VX_Cache_Bank
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.CACHE_BANKS(CACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(
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.clk (clk),
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.rst (rst),
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// Inputs
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.addr (actual_index),
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.we (we),
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41
rtl/cache/VX_cache_data.v
vendored
41
rtl/cache/VX_cache_data.v
vendored
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@ -11,7 +11,7 @@ module VX_cache_data
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parameter NUM_WORDS_PER_BLOCK = 4
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)
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(
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input wire clk, // Clock
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input wire clk, rst, // Clock
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// Addr
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input wire[`CACHE_IND_SIZE_RNG] addr,
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@ -56,29 +56,30 @@ module VX_cache_data
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assign valid_use = valid[addr];
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assign dirty_use = dirty[addr];
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always @(posedge clk) begin : dirty_update
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if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
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end
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integer f;
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always @(posedge clk) begin : data_update
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for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
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if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
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if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
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if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
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if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
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integer ini_ind;
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always @(posedge clk, posedge rst) begin : update_all
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if (rst) begin
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for (ini_ind = 0; ini_ind < NUMBER_INDEXES; ini_ind=ini_ind+1) begin
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data[ini_ind] = 0;
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tag[ini_ind] = 0;
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valid[ini_ind] = 0;
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dirty[ini_ind] = 0;
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end
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end else begin
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if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
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if (evict) tag[addr] <= tag_write;
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if (evict) valid[addr] <= 1;
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for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
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if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
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if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
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if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
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if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
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end
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end
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end
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always @(posedge clk) begin : tag_update
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if (evict) tag[addr] <= tag_write;
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end
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always @(posedge clk) begin : valid_update
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if (evict) valid[addr] <= 1;
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end
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`else
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36
rtl/cache/VX_d_cache.v
vendored
36
rtl/cache/VX_d_cache.v
vendored
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@ -206,19 +206,36 @@ module VX_d_cache
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// Handle if there is more than one miss
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assign new_stored_valid = use_valid & (~threads_serviced_Qual);
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///////////////////////////////////////////////////////////////////////
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genvar cur_t;
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always @(posedge clk) begin
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state <= new_state;
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integer init_b;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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final_data_read <= 0;
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new_final_data_read = 0;
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state <= 0;
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stored_valid <= 0;
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// eviction_addr_per_bank <= 0;
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miss_addr <= 0;
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evict_addr <= 0;
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// threads_serviced_Qual = 0;
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// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
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// begin
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// debug_hit_per_bank_mask[init_b] <= 0;
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// end
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end else begin
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state <= new_state;
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stored_valid <= new_stored_valid;
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stored_valid <= new_stored_valid;
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if (miss_found) begin
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miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
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evict_addr <= eviction_addr_per_bank[miss_bank_index];
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if (miss_found) begin
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miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
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evict_addr <= eviction_addr_per_bank[miss_bank_index];
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end
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final_data_read <= new_final_data_read_Qual;
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end
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final_data_read <= new_final_data_read_Qual;
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end
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@ -250,6 +267,7 @@ module VX_d_cache
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|||
.CACHE_BANKS(CACHE_BANKS)) bank_structure
|
||||
(
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.state (state),
|
||||
.valid_in (use_valid_in),
|
||||
.actual_index (cache_index),
|
||||
|
|
|
|||
|
|
@ -1,18 +1,4 @@
|
|||
###############################################################################
|
||||
#
|
||||
# ICARUS VERILOG & GTKWAVE MAKEFILE
|
||||
# MADE BY WILLIAM GIBB FOR HACDC
|
||||
# williamgibb@gmail.com
|
||||
#
|
||||
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
|
||||
# "make check" - compiles your verilog design - good for checking code
|
||||
# "make simulate" - compiles your design+TB & simulates your design
|
||||
# "make display" - compiles, simulates and displays waveforms
|
||||
#
|
||||
###############################################################################
|
||||
#
|
||||
# CHANGE THESE THREE LINES FOR YOUR DESIGN
|
||||
#
|
||||
|
||||
|
||||
ALL:sim
|
||||
|
||||
|
|
@ -86,13 +72,14 @@ SRC = \
|
|||
../shared_memory/VX_bank_valids.v \
|
||||
../shared_memory/VX_priority_encoder_sm.v \
|
||||
../shared_memory/VX_shared_memory.v \
|
||||
../shared_memory/VX_shared_memory_block.v
|
||||
../shared_memory/VX_shared_memory_block.v \
|
||||
vortex_dpi.cpp
|
||||
|
||||
|
||||
CMD= \
|
||||
-do "vcd file vortex.vcd; \
|
||||
vcd add -r vortex_tb; \
|
||||
run; \
|
||||
vcd add -r /vortex/*; \
|
||||
run -all; \
|
||||
quit -f"
|
||||
|
||||
|
||||
|
|
@ -103,26 +90,11 @@ LIB = vortex_lib
|
|||
# LOG=-logfile vortex_tb.log
|
||||
LOG=
|
||||
|
||||
# ../shared_memory/VX_set_bit.v \
|
||||
# ../cache/bank.v \
|
||||
# ../cache/VX_d_cache_tb.v \
|
||||
# ../cache/VX_d_cache_encapsulate.v \
|
||||
# ../VX_rename.v \
|
||||
# ../cache/VX_Cache_Block_DM.v \
|
||||
# ../VX_one_counter.v \
|
||||
###############################################################################
|
||||
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
|
||||
###############################################################################
|
||||
#TOOLS
|
||||
#TOOL OUTPUT
|
||||
###############################################################################
|
||||
#MAKE DIRECTIVES
|
||||
|
||||
# setup: source cshrc.modelsim
|
||||
# vlib
|
||||
|
||||
comp:
|
||||
vlog $(OPT) -work $(LIB) $(SRC)
|
||||
vlog -O0 $(OPT) -work $(LIB) $(SRC)
|
||||
|
||||
|
||||
sim: comp
|
||||
|
|
|
|||
145
rtl/modelsim/vortex_dpi.cpp
Normal file
145
rtl/modelsim/vortex_dpi.cpp
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
// #include <iostream>
|
||||
|
||||
// #include "VX_define.h"
|
||||
|
||||
|
||||
#include <../simulate/ram.h>
|
||||
#include <stdio.h>
|
||||
#include "svdpi.h"
|
||||
|
||||
#include "../simulate/VX_define.h"
|
||||
|
||||
extern "C" {
|
||||
void load_file(char * filename);
|
||||
void ibus_driver(int pc_addr, int * instruction);
|
||||
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready);
|
||||
void io_handler(bool io_valid, int io_data);
|
||||
}
|
||||
|
||||
RAM ram;
|
||||
|
||||
unsigned getIndex(int r, int c, int numCols)
|
||||
{
|
||||
return (r * numCols) + c;
|
||||
}
|
||||
|
||||
|
||||
void load_file(char * filename)
|
||||
{
|
||||
printf("\n\n\n\n**********************\n");
|
||||
// printf("Inside load_file\n");
|
||||
loadHexImpl(filename, &ram);
|
||||
// printf("Filename: %s\n", filename);
|
||||
}
|
||||
|
||||
void ibus_driver(int pc_addr, int * instruction)
|
||||
{
|
||||
// printf("Inside ibus_driver\n");
|
||||
uint32_t curr_inst = 0;
|
||||
curr_inst = 0xdeadbeef;
|
||||
|
||||
|
||||
uint32_t u_pc_addr = (uint32_t) (pc_addr);
|
||||
|
||||
ram.getWord(u_pc_addr, &curr_inst);
|
||||
|
||||
// printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction);
|
||||
|
||||
(*instruction) = curr_inst;
|
||||
|
||||
}
|
||||
|
||||
bool refill;
|
||||
unsigned refill_addr;
|
||||
|
||||
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready)
|
||||
{
|
||||
// printf("Inside dbus_driver\n");
|
||||
|
||||
(*i_m_ready )= 0;
|
||||
for (int i = 0; i < CACHE_NUM_BANKS; i++)
|
||||
{
|
||||
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
|
||||
{
|
||||
i_m_readdata[getIndex(i,j, CACHE_WORDS_PER_BLOCK)] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (refill)
|
||||
{
|
||||
refill = false;
|
||||
|
||||
*i_m_ready = 1;
|
||||
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
|
||||
{
|
||||
unsigned new_addr = refill_addr + (4*curr_e);
|
||||
|
||||
|
||||
unsigned addr_without_byte = new_addr >> 2;
|
||||
unsigned bank_num = addr_without_byte & 0x7;
|
||||
unsigned addr_wihtout_bank = addr_without_byte >> 3;
|
||||
unsigned offset_num = addr_wihtout_bank & 0x3;
|
||||
|
||||
unsigned value;
|
||||
ram.getWord(new_addr, &value);
|
||||
|
||||
// printf("-------- (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
|
||||
i_m_readdata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)] = value;
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (o_m_valid)
|
||||
{
|
||||
// printf("Valid o_m_valid\n");
|
||||
if (o_m_read_or_write)
|
||||
{
|
||||
// printf("Valid write\n");
|
||||
|
||||
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
|
||||
{
|
||||
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
|
||||
|
||||
|
||||
unsigned addr_without_byte = new_addr >> 2;
|
||||
unsigned bank_num = addr_without_byte & 0x7;
|
||||
unsigned addr_wihtout_bank = addr_without_byte >> 3;
|
||||
unsigned offset_num = addr_wihtout_bank & 0x3;
|
||||
|
||||
|
||||
unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)];
|
||||
|
||||
ram.writeWord( new_addr, &new_value);
|
||||
|
||||
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
|
||||
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
refill = true;
|
||||
refill_addr = o_m_read_addr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void io_handler(bool io_valid, int io_data)
|
||||
{
|
||||
// printf("Inside io_handler\n");
|
||||
if (io_valid)
|
||||
{
|
||||
uint32_t data_write = (uint32_t) (io_data);
|
||||
|
||||
char c = (char) data_write;
|
||||
printf("%c", c);
|
||||
printf("YOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYO\n");
|
||||
fflush(stdout);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,8 +1,29 @@
|
|||
// `include "../VX_define.v"
|
||||
// `include "../Vortex.v"
|
||||
|
||||
`include "../VX_define.v"
|
||||
|
||||
`define NUMBER_BANKS 8
|
||||
`define NUM_WORDS_PER_BLOCK 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
import "DPI-C" load_file = function void load_file(input string filename);
|
||||
|
||||
import "DPI-C" ibus_driver = function void ibus_driver(input int pc_addr,
|
||||
output int instruction);
|
||||
|
||||
import "DPI-C" dbus_driver = function void dbus_driver( input int o_m_read_addr,
|
||||
input int o_m_evict_addr,
|
||||
input reg o_m_valid,
|
||||
input reg [31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
|
||||
input reg o_m_read_or_write,
|
||||
|
||||
// Rsp
|
||||
output reg [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
|
||||
output reg i_m_ready);
|
||||
|
||||
import "DPI-C" io_handler = function void io_handler(input reg io_valid, input int io_data);
|
||||
|
||||
|
||||
module vortex_tb (
|
||||
|
||||
);
|
||||
|
|
@ -26,21 +47,21 @@ module vortex_tb (
|
|||
reg i_m_ready;
|
||||
reg out_ebreak;
|
||||
|
||||
integer temp;
|
||||
initial begin
|
||||
// $dumpfile("vortex2.vcd");
|
||||
$dumpvars(0, vortex);
|
||||
for (temp = 0; temp < 10; temp=temp+1)
|
||||
begin
|
||||
|
||||
if (temp == 0) begin
|
||||
icache_response_instruction = 32'h00000513;
|
||||
$display("Cycle 1");
|
||||
end if (temp == 1) begin
|
||||
$display("Cycle 2",);
|
||||
icache_response_instruction = 32'h0005006b;
|
||||
end
|
||||
end
|
||||
reg[31:0] hi;
|
||||
|
||||
integer temp;
|
||||
integer num_cycles;
|
||||
|
||||
initial begin
|
||||
// $fdumpfile("vortex1.vcd");
|
||||
load_file("../../kernel/vortex_test.hex");
|
||||
$dumpvars(0, vortex_tb);
|
||||
reset = 1;
|
||||
clk = 0;
|
||||
#5 reset = 1;
|
||||
clk = 1;
|
||||
num_cycles = 0;
|
||||
end
|
||||
|
||||
Vortex vortex(
|
||||
|
|
@ -61,6 +82,37 @@ module vortex_tb (
|
|||
);
|
||||
|
||||
|
||||
always @(clk) #5 clk <= ~clk;
|
||||
always @(clk, posedge reset) begin
|
||||
// $display("FROM ALWAYS");
|
||||
// $display("num_cycles: %d",num_cycles);
|
||||
num_cycles = num_cycles + 1;
|
||||
if (num_cycles == 1000) begin
|
||||
// $dumpall;
|
||||
// $dumpflush;
|
||||
// $finish;
|
||||
end
|
||||
// if (num_cycles == 1000) $stop;
|
||||
if (reset) begin
|
||||
reset = 0;
|
||||
clk = 0;
|
||||
end
|
||||
|
||||
if (clk == 0) begin
|
||||
ibus_driver(icache_request_pc_address, icache_response_instruction);
|
||||
dbus_driver(o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
|
||||
io_handler(io_valid, io_data);
|
||||
end
|
||||
|
||||
// $display("clk: %d, out_ebreak: %d",clk, out_ebreak);
|
||||
#5 clk <= ~clk;
|
||||
if (out_ebreak) $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -7,8 +7,8 @@ module VX_priority_encoder_sm
|
|||
)
|
||||
(
|
||||
//INPUTS
|
||||
input wire clk,
|
||||
//input wire reset,
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire[`NT_M1:0] in_valid,
|
||||
input wire[`NT_M1:0][31:0] in_address,
|
||||
input wire[`NT_M1:0][31:0] in_data,
|
||||
|
|
@ -25,6 +25,8 @@ module VX_priority_encoder_sm
|
|||
);
|
||||
|
||||
reg[`NT_M1:0] left_requests;
|
||||
reg[`NT_M1:0] serviced;
|
||||
|
||||
|
||||
wire[`NT_M1:0] use_valid;
|
||||
|
||||
|
|
@ -71,7 +73,6 @@ module VX_priority_encoder_sm
|
|||
assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
|
||||
end
|
||||
|
||||
reg[`NT_M1:0] serviced;
|
||||
integer curr_b;
|
||||
always @(*) begin
|
||||
serviced = 0;
|
||||
|
|
@ -91,9 +92,14 @@ module VX_priority_encoder_sm
|
|||
|
||||
// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!stall) left_requests <= 0;
|
||||
else left_requests <= new_left_requests;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
left_requests <= 0;
|
||||
serviced = 0;
|
||||
end else begin
|
||||
if (!stall) left_requests <= 0;
|
||||
else left_requests <= new_left_requests;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -8,6 +8,7 @@ module VX_shared_memory
|
|||
(
|
||||
//INPUTS
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire[`NT_M1:0] in_valid,
|
||||
input wire[`NT_M1:0][31:0] in_address,
|
||||
input wire[`NT_M1:0][31:0] in_data,
|
||||
|
|
@ -52,7 +53,7 @@ genvar f;
|
|||
|
||||
VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
|
||||
.clk(clk),
|
||||
//.reset(reset),
|
||||
.reset(reset),
|
||||
.in_valid(orig_in_valid),
|
||||
.in_address(in_address),
|
||||
.in_data(in_data),
|
||||
|
|
@ -71,12 +72,13 @@ integer i;
|
|||
generate
|
||||
for(j=0; j<= NB; j=j+1) begin
|
||||
VX_shared_memory_block vx_shared_memory_block(
|
||||
.clk(clk),
|
||||
.addr(block_addr[j]),
|
||||
.wdata(block_wdata[j]),
|
||||
.we(block_we[j]),
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.addr (block_addr[j]),
|
||||
.wdata (block_wdata[j]),
|
||||
.we (block_we[j]),
|
||||
.shm_write(shm_write),
|
||||
.data_out(block_rdata[j])
|
||||
.data_out (block_rdata[j])
|
||||
);
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
module VX_shared_memory_block (
|
||||
input clk, // Clock
|
||||
input wire[6:0] addr,
|
||||
input wire[3:0][31:0] wdata,
|
||||
input wire[1:0] we,
|
||||
input wire shm_write,
|
||||
input wire clk, // Clock
|
||||
input wire reset,
|
||||
input wire[6:0] addr,
|
||||
input wire[3:0][31:0] wdata,
|
||||
input wire[1:0] we,
|
||||
input wire shm_write,
|
||||
|
||||
output wire[3:0][31:0] data_out
|
||||
|
||||
|
|
@ -12,12 +13,17 @@ module VX_shared_memory_block (
|
|||
|
||||
`ifndef SYN
|
||||
|
||||
logic [3:0][31:0] shared_memory[127:0];
|
||||
reg[3:0][31:0] shared_memory[127:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(shm_write) begin
|
||||
integer curr_ind;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
|
||||
begin
|
||||
shared_memory[curr_ind] = 0;
|
||||
end
|
||||
end else if(shm_write) begin
|
||||
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
|
|
|
|||
|
|
@ -2,9 +2,13 @@
|
|||
|
||||
#define __RAM__
|
||||
|
||||
#include "string.h"
|
||||
// #include "string.h"
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <cstdint>
|
||||
// #include <cstdint>
|
||||
|
||||
// #define NULL 0
|
||||
|
||||
class RAM{
|
||||
public:
|
||||
uint8_t* mem[1 << 12];
|
||||
|
|
@ -157,11 +161,12 @@ uint32_t hToI(char *c, uint32_t size) {
|
|||
|
||||
|
||||
|
||||
void loadHexImpl(std::string path,RAM* mem) {
|
||||
void loadHexImpl(char * path,RAM* mem) {
|
||||
mem->clear();
|
||||
FILE *fp = fopen(&path[0], "r");
|
||||
if(fp == 0){
|
||||
std::cout << path << " not found" << std::endl;
|
||||
printf("Path not found %s\n", path);
|
||||
// std::cout << path << " not found" << std::endl;
|
||||
}
|
||||
//Preload 0x0 <-> 0x80000000 jumps
|
||||
((uint32_t*)mem->get(0))[1] = 0xf1401073;
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ Vortex::~Vortex()
|
|||
|
||||
void Vortex::ProcessFile(void)
|
||||
{
|
||||
loadHexImpl(this->instruction_file_name, &this->ram);
|
||||
loadHexImpl("../../kernel/vortex_test.hex", &this->ram);
|
||||
}
|
||||
|
||||
void Vortex::print_stats(bool cycle_test)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue