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minor update

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This commit is contained in:
Blaise Tine 2023-03-25 17:25:58 -04:00
parent e7b9f311a9
commit 1433e553a0
3 changed files with 11 additions and 17 deletions
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6
hw/rtl/cache/VX_bank.sv vendored
View file

@ -241,8 +241,8 @@ module VX_bank #(
wire tag_match_st0;
// added for associativity
wire [`WAY_SEL_BITS-1:0] way_sel_st0;
wire [`WAY_SEL_BITS-1:0] way_sel_st1;
wire [NUM_WAYS-1:0] way_sel_st0;
wire [NUM_WAYS-1:0] way_sel_st1;
VX_tag_access #(
.INSTANCE_ID(INSTANCE_ID),
@ -279,7 +279,7 @@ module VX_bank #(
wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = is_read_st0 ? mshr_alloc_id : mshr_id_st0;
VX_pipe_register #(
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + `WAY_SEL_BITS + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SEL_WIDTH + WORD_SIZE + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + 1),
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + NUM_WAYS + `LINE_ADDR_WIDTH + `LINE_WIDTH + NUM_PORTS * (WORD_SEL_WIDTH + WORD_SIZE + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + 1),
.RESETW (1)
) pipe_reg1 (
.clk (clk),

6
hw/rtl/cache/VX_data_access.sv vendored
View file

@ -38,7 +38,7 @@ module VX_data_access #(
input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen,
input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data,
input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data,
input wire [`WAY_SEL_BITS-1:0] way_sel,
input wire [NUM_WAYS-1:0] way_sel,
output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data
);
@ -106,7 +106,7 @@ module VX_data_access #(
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.write ((write || fill) && (way_sel == `WAY_SEL_BITS'(i))),
.write ((write || fill) && way_sel[i]),
.wren (wren),
.addr (line_addr),
.wdata (wdata),
@ -114,7 +114,7 @@ module VX_data_access #(
);
end
VX_mux #(
VX_onehot_mux #(
.DATAW (`WORDS_PER_LINE * `WORD_WIDTH),
.N (NUM_WAYS)
) rdata_select (

16
hw/rtl/cache/VX_tag_access.sv vendored
View file

@ -30,7 +30,7 @@ module VX_tag_access #(
input wire [`LINE_ADDR_WIDTH-1:0] addr,
input wire fill,
input wire init,
output wire [`WAY_SEL_BITS-1:0] way_sel,
output wire [NUM_WAYS-1:0] way_sel,
output wire tag_match
);
`UNUSED_SPARAM (INSTANCE_ID)
@ -87,25 +87,19 @@ module VX_tag_access #(
assign tag_match = (| tag_matches);
// return the selected way
VX_onehot_encoder #(
.N (NUM_WAYS)
) way_encoder (
.data_in (fill_way | tag_matches),
.data_out (way_sel),
`UNUSED_PIN (valid_out)
);
assign way_sel = fill_way | tag_matches;
`ifdef DBG_TRACE_CACHE_TAG
always @(posedge clk) begin
if (fill && ~stall) begin
`TRACE(3, ("%d: %s:%0d tag-fill: addr=0x%0h, way=%0d, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), way_sel, line_addr, line_tag));
`TRACE(3, ("%d: %s:%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), way_sel, line_addr, line_tag));
end
if (init) begin
`TRACE(3, ("%d: %s:%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr));
end
if (lookup && ~stall) begin
if (tag_match) begin
`TRACE(3, ("%d: %s:%0d tag-hit: addr=0x%0h, way=%0d, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), way_sel, line_addr, line_tag, req_uuid));
`TRACE(3, ("%d: %s:%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), way_sel, line_addr, line_tag, req_uuid));
end else begin
`TRACE(3, ("%d: %s:%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag, req_uuid));
end