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ram blocks refactoring

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This commit is contained in:
Blaise Tine 2023-03-25 16:42:11 -04:00
parent aa3d4de3d2
commit e7b9f311a9
13 changed files with 240 additions and 397 deletions
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2
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -749,7 +749,6 @@ VX_fifo_queue #(
`UNUSED_PIN (size)
);
`ifdef VERILATOR
`DEBUG_BLOCK(
reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask;
always @(posedge clk) begin
@ -767,7 +766,6 @@ VX_fifo_queue #(
end
end
)
`endif
// CCI-P Write Request //////////////////////////////////////////////////////////

11
hw/rtl/cache/VX_data_access.sv vendored
View file

@ -79,13 +79,13 @@ module VX_data_access #(
wren_r[wsel] = byteen;
end
end
assign wdata = write ? wdata_r : fill_data;
assign wren = write ? wren_r : {BYTEENW{fill}};
assign wdata = fill ? fill_data : wdata_r;
assign wren = fill ? {BYTEENW{fill}} : wren_r;
end else begin
`UNUSED_VAR (wsel)
`UNUSED_VAR (pmask)
assign wdata = write ? write_data : fill_data;
assign wren = write ? byteen : {BYTEENW{fill}};
assign wdata = fill ? fill_data : write_data;
assign wren = fill ? {BYTEENW{fill}} : byteen;
end
end else begin
`UNUSED_VAR (write)
@ -106,8 +106,9 @@ module VX_data_access #(
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.write ((write || fill) && (way_sel == `WAY_SEL_BITS'(i))),
.wren (wren),
.addr (line_addr),
.wren (wren & {BYTEENW{way_sel == `WAY_SEL_BITS'(i)}}),
.wdata (wdata),
.rdata (per_way_rdata[i])
);

7
hw/rtl/cache/VX_miss_resrv.sv vendored
View file

@ -181,10 +181,11 @@ module VX_miss_resrv #(
.LUTRAM (1)
) entries (
.clk (clk),
.waddr (allocate_id_r),
.raddr (dequeue_id_r),
.wren (allocate_valid),
.write (allocate_valid),
`UNUSED_PIN (wren),
.waddr (allocate_id_r),
.wdata (allocate_data),
.raddr (dequeue_id_r),
.rdata (dequeue_data)
);

5
hw/rtl/cache/VX_shared_mem.sv vendored
View file

@ -150,8 +150,6 @@ module VX_shared_mem #(
// Generate memory banks
for (genvar i = 0; i < NUM_BANKS; ++i) begin
wire [WORD_SIZE-1:0] wren = {WORD_SIZE{per_bank_req_valid[i] && per_bank_req_rw[i]}}
& per_bank_req_byteen[i];
VX_sp_ram #(
.DATAW (WORD_WIDTH),
.SIZE (WORDS_PER_BANK),
@ -159,7 +157,8 @@ module VX_shared_mem #(
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.wren (wren),
.write (per_bank_req_valid[i] && per_bank_req_rw[i]),
.wren (per_bank_req_byteen[i]),
.addr (per_bank_req_addr[i]),
.wdata (per_bank_req_data[i]),
.rdata (per_bank_rsp_data[i])

7
hw/rtl/cache/VX_tag_access.sv vendored
View file

@ -72,9 +72,10 @@ module VX_tag_access #(
.SIZE (`LINES_PER_BANK),
.NO_RWCHECK (1)
) tag_store (
.clk (clk),
.addr (line_addr),
.wren (fill_way[i] || init),
.clk (clk),
.write (fill_way[i] || init),
`UNUSED_PIN (wren),
.addr (line_addr),
.wdata ({~init, line_tag}),
.rdata ({read_valid, read_tag})
);

13
hw/rtl/core/VX_gpr_stage.sv
View file

@ -23,9 +23,9 @@ module VX_gpr_stage #(
// ensure r0 never gets written, which can happen before the reset
wire write_enable = writeback_if.valid && (writeback_if.rd != 0);
wire [`NUM_THREADS-1:0] wren;
wire [`NUM_THREADS-1:0] write;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign wren[i] = write_enable && writeback_if.tmask[i];
assign write[i] = write_enable && writeback_if.tmask[i];
end
wire [RAM_ADDRW-1:0] waddr, raddr1, raddr2;
@ -49,7 +49,8 @@ module VX_gpr_stage #(
.INIT_VALUE (0)
) dp_ram1 (
.clk (clk),
.wren (wren[i]),
.write (write[i]),
`UNUSED_PIN (wren),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.raddr (raddr1),
@ -63,7 +64,8 @@ module VX_gpr_stage #(
.INIT_VALUE (0)
) dp_ram2 (
.clk (clk),
.wren (wren[i]),
.write (write[i]),
`UNUSED_PIN (wren),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.raddr (raddr2),
@ -87,7 +89,8 @@ module VX_gpr_stage #(
.INIT_VALUE (0)
) dp_ram3 (
.clk (clk),
.wren (wren[i]),
.write (write[i]),
`UNUSED_PIN (wren),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.raddr (raddr3),

3
hw/rtl/core/VX_icache_stage.sv
View file

@ -52,7 +52,8 @@ module VX_icache_stage #(
.LUTRAM (1)
) tag_store (
.clk (clk),
.wren (icache_req_fire),
.write (icache_req_fire),
`UNUSED_PIN (wren),
.waddr (req_tag),
.wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}),
.raddr (rsp_tag),

3
hw/rtl/core/VX_ipdom_stack.sv
View file

@ -58,7 +58,8 @@ module VX_ipdom_stack #(
.LUTRAM (1)
) store (
.clk (clk),
.wren (push),
.write (push),
`UNUSED_PIN (wren),
.waddr (wr_ptr),
.wdata ({q2, q1}),
.raddr (rd_ptr),

321
hw/rtl/libs/VX_dp_ram.sv
View file

@ -4,7 +4,7 @@
module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter WRENW = 1,
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter LUTRAM = 0,
@ -14,6 +14,7 @@ module VX_dp_ram #(
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire write,
input wire [WRENW-1:0] wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
@ -34,187 +35,221 @@ module VX_dp_ram #(
end \
end
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`ifdef SYNTHESIS
if (WRENW > 1) begin
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end else begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end
end
end
`else
// default synthesis
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
assign rdata = ram[raddr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end
`endif
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r;
// (WRENW == 1)
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
if (write) begin
ram[waddr] <= wdata;
end
rdata_r <= ram[raddr];
end
assign rdata = ram[raddr];
assign rdata = rdata_r;
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
if (write) begin
ram[waddr] <= wdata;
end
end
assign rdata = ram[raddr];
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
rdata_r <= ram[raddr];
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
end
assign rdata = ram[raddr];
end
end
end
end
end
`else
// RAM emulation
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if ((WRENW == 1) || wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
rdata_r <= ram[raddr];
end
@ -224,9 +259,11 @@ module VX_dp_ram #(
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if ((WRENW == 1) || wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
prev_write <= (| wren);
prev_data <= ram[waddr];

6
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -166,7 +166,8 @@ module VX_fifo_queue #(
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.wren (push),
.write (push),
`UNUSED_PIN (wren),
.waddr (wr_ptr_r),
.wdata (data_in),
.raddr (rd_ptr_r),
@ -208,7 +209,8 @@ module VX_fifo_queue #(
.LUTRAM (LUTRAM)
) dp_ram (
.clk (clk),
.wren (push),
.write (push),
`UNUSED_PIN (wren),
.waddr (wr_ptr_r),
.wdata (data_in),
.raddr (rd_ptr_n_r),

3
hw/rtl/libs/VX_index_buffer.sv
View file

@ -74,7 +74,8 @@ module VX_index_buffer #(
.LUTRAM (LUTRAM)
) data_table (
.clk (clk),
.wren (acquire_slot),
.write (acquire_slot),
`UNUSED_PIN (wren),
.waddr (write_addr_r),
.wdata (write_data),
.raddr (read_addr),

249
hw/rtl/libs/VX_sp_ram.sv
View file

@ -13,236 +13,33 @@ module VX_sp_ram #(
parameter [DATAW-1:0] INIT_VALUE = 0,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire clk,
input wire write,
input wire [WRENW-1:0] wren,
input wire [ADDRW-1:0] addr,
input wire [DATAW-1:0] wdata,
output wire [DATAW-1:0] rdata
);
localparam WSELW = DATAW / WRENW;
`STATIC_ASSERT((WRENW * WSELW == DATAW), ("invalid parameter"))
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin \
initial begin \
if (INIT_FILE != "") begin \
$readmemh(INIT_FILE, ram); \
end else begin \
for (integer i = 0; i < SIZE; ++i) \
ram[i] = INIT_VALUE; \
end \
end \
end
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
assign rdata = rdata_r;
end else begin
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end
end
end
`else
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
assign rdata = rdata_r;
end else begin
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
prev_write <= (| wren);
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end
`endif
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.WRENW (WRENW),
.OUT_REG (OUT_REG),
.NO_RWCHECK (NO_RWCHECK),
.LUTRAM (LUTRAM),
.INIT_ENABLE (INIT_ENABLE),
.INIT_FILE (INIT_FILE),
.INIT_VALUE (INIT_VALUE),
.ADDRW (ADDRW)
) dp_ram (
.clk (clk),
.write (write),
.wren (wren),
.waddr (addr),
.wdata (wdata),
.raddr (addr),
.rdata (rdata)
);
endmodule
`TRACING_ON

7
hw/rtl/raster_unit/VX_raster_csr.sv
View file

@ -25,7 +25,7 @@ module VX_raster_csr #(
raster_csrs_t [`NUM_THREADS-1:0] wdata;
raster_csrs_t [`NUM_THREADS-1:0] rdata;
wire [`NUM_THREADS-1:0] wren;
wire [`NUM_THREADS-1:0] write;
wire [NW_WIDTH-1:0] waddr;
wire [NW_WIDTH-1:0] raddr;
@ -37,7 +37,8 @@ module VX_raster_csr #(
.LUTRAM (1)
) stamp_store (
.clk (clk),
.wren (wren[i]),
.write (write[i]),
`UNUSED_PIN (wren),
.waddr (waddr),
.wdata (wdata[i]),
.raddr (raddr),
@ -50,7 +51,7 @@ module VX_raster_csr #(
assign waddr = write_wid;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign wren[i] = write_enable && write_tmask[i];
assign write[i] = write_enable && write_tmask[i];
assign wdata[i].pos_mask = {write_data[i].pos_y, write_data[i].pos_x, write_data[i].mask};
assign wdata[i].bcoords = write_data[i].bcoords;
end