mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
parent
d6770f7adc
commit
156707bbec
11 changed files with 101 additions and 99 deletions
62
hw/rtl/cache/VX_cache.sv
vendored
62
hw/rtl/cache/VX_cache.sv
vendored
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@ -318,21 +318,21 @@ module VX_cache import VX_gpu_pkg::*; #(
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end
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// Banks access
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for (genvar i = 0; i < NUM_BANKS; ++i) begin : banks
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for (genvar bank_id = 0; bank_id < NUM_BANKS; ++bank_id) begin : banks
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wire [`CS_LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
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wire curr_bank_mem_rsp_valid;
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if (NUM_BANKS == 1) begin
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assign curr_bank_mem_rsp_valid = mem_rsp_valid_s;
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end else begin
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assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == i);
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assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == bank_id);
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end
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`RESET_RELAY (bank_reset, reset);
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VX_cache_bank #(
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.BANK_ID (i),
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.INSTANCE_ID (INSTANCE_ID),
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.BANK_ID (bank_id),
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.INSTANCE_ID ($sformatf("%s-bank%0d", INSTANCE_ID, bank_id)),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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@ -352,44 +352,44 @@ module VX_cache import VX_gpu_pkg::*; #(
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.reset (bank_reset),
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`ifdef PERF_ENABLE
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.perf_read_misses (perf_read_miss_per_bank[i]),
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.perf_write_misses (perf_write_miss_per_bank[i]),
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.perf_mshr_stalls (perf_mshr_stall_per_bank[i]),
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.perf_read_misses (perf_read_miss_per_bank[bank_id]),
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.perf_write_misses (perf_write_miss_per_bank[bank_id]),
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.perf_mshr_stalls (perf_mshr_stall_per_bank[bank_id]),
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`endif
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// Core request
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.core_req_valid (per_bank_core_req_valid[i]),
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.core_req_addr (per_bank_core_req_addr[i]),
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.core_req_rw (per_bank_core_req_rw[i]),
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.core_req_wsel (per_bank_core_req_wsel[i]),
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.core_req_byteen (per_bank_core_req_byteen[i]),
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.core_req_data (per_bank_core_req_data[i]),
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.core_req_tag (per_bank_core_req_tag[i]),
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.core_req_idx (per_bank_core_req_idx[i]),
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.core_req_ready (per_bank_core_req_ready[i]),
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.core_req_valid (per_bank_core_req_valid[bank_id]),
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.core_req_addr (per_bank_core_req_addr[bank_id]),
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.core_req_rw (per_bank_core_req_rw[bank_id]),
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.core_req_wsel (per_bank_core_req_wsel[bank_id]),
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.core_req_byteen (per_bank_core_req_byteen[bank_id]),
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.core_req_data (per_bank_core_req_data[bank_id]),
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.core_req_tag (per_bank_core_req_tag[bank_id]),
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.core_req_idx (per_bank_core_req_idx[bank_id]),
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.core_req_ready (per_bank_core_req_ready[bank_id]),
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// Core response
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.core_rsp_valid (per_bank_core_rsp_valid[i]),
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.core_rsp_data (per_bank_core_rsp_data[i]),
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.core_rsp_tag (per_bank_core_rsp_tag[i]),
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.core_rsp_idx (per_bank_core_rsp_idx[i]),
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.core_rsp_ready (per_bank_core_rsp_ready[i]),
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.core_rsp_valid (per_bank_core_rsp_valid[bank_id]),
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.core_rsp_data (per_bank_core_rsp_data[bank_id]),
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.core_rsp_tag (per_bank_core_rsp_tag[bank_id]),
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.core_rsp_idx (per_bank_core_rsp_idx[bank_id]),
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.core_rsp_ready (per_bank_core_rsp_ready[bank_id]),
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// Memory request
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.mem_req_valid (per_bank_mem_req_valid[i]),
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.mem_req_valid (per_bank_mem_req_valid[bank_id]),
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.mem_req_addr (curr_bank_mem_req_addr),
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.mem_req_rw (per_bank_mem_req_rw[i]),
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.mem_req_wsel (per_bank_mem_req_wsel[i]),
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.mem_req_byteen (per_bank_mem_req_byteen[i]),
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.mem_req_data (per_bank_mem_req_data[i]),
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.mem_req_id (per_bank_mem_req_id[i]),
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.mem_req_ready (per_bank_mem_req_ready[i]),
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.mem_req_rw (per_bank_mem_req_rw[bank_id]),
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.mem_req_wsel (per_bank_mem_req_wsel[bank_id]),
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.mem_req_byteen (per_bank_mem_req_byteen[bank_id]),
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.mem_req_data (per_bank_mem_req_data[bank_id]),
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.mem_req_id (per_bank_mem_req_id[bank_id]),
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.mem_req_ready (per_bank_mem_req_ready[bank_id]),
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// Memory response
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.mem_rsp_valid (curr_bank_mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data_s),
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.mem_rsp_id (`CS_MEM_TAG_TO_REQ_ID(mem_rsp_tag_s)),
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.mem_rsp_ready (per_bank_mem_rsp_ready[i]),
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.mem_rsp_ready (per_bank_mem_rsp_ready[bank_id]),
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// initialization
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.init_enable (init_enable),
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@ -397,9 +397,9 @@ module VX_cache import VX_gpu_pkg::*; #(
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);
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if (NUM_BANKS == 1) begin
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assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr;
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assign per_bank_mem_req_addr[bank_id] = curr_bank_mem_req_addr;
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end else begin
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assign per_bank_mem_req_addr[i] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i);
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assign per_bank_mem_req_addr[bank_id] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, bank_id);
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end
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end
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24
hw/rtl/cache/VX_cache_bank.sv
vendored
24
hw/rtl/cache/VX_cache_bank.sv
vendored
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@ -245,7 +245,7 @@ module VX_cache_bank #(
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`RESET_RELAY (tag_reset, reset);
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VX_cache_tags #(
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.INSTANCE_ID(INSTANCE_ID),
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.INSTANCE_ID($sformatf("%s-tags", INSTANCE_ID)),
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.BANK_ID (BANK_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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@ -322,7 +322,7 @@ module VX_cache_bank #(
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`RESET_RELAY (data_reset, reset);
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VX_cache_data #(
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.INSTANCE_ID (INSTANCE_ID),
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.INSTANCE_ID ($sformatf("%s-data", INSTANCE_ID)),
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.BANK_ID (BANK_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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@ -372,7 +372,7 @@ module VX_cache_bank #(
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`RESET_RELAY (mshr_reset, reset);
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VX_cache_mshr #(
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.INSTANCE_ID (INSTANCE_ID),
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.INSTANCE_ID ($sformatf("%s-mshr", INSTANCE_ID)),
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.BANK_ID (BANK_ID),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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@ -519,31 +519,31 @@ module VX_cache_bank #(
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&& ~(replay_fire || mem_rsp_fire || core_req_fire);
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always @(posedge clk) begin
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if (pipeline_stall) begin
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`TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsp_queue_stall, mreq_queue_alm_full, mshr_alm_full));
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`TRACE(3, ("%d: *** %s stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, crsp_queue_stall, mreq_queue_alm_full, mshr_alm_full));
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end
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if (init_enable) begin
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`TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID)));
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`TRACE(2, ("%d: %s init: addr=0x%0h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID)));
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end
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if (mem_rsp_fire) begin
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`TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data));
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`TRACE(2, ("%d: %s fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data));
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end
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if (replay_fire) begin
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`TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel));
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`TRACE(2, ("%d: %s mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel));
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end
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if (core_req_fire) begin
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if (core_req_rw)
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`TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel));
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`TRACE(2, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel));
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else
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`TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel));
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`TRACE(2, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel));
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end
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if (crsp_queue_fire) begin
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`TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsp_queue_tag, crsp_queue_idx, crsp_queue_data, req_uuid_st1));
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`TRACE(2, ("%d: %s core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsp_queue_tag, crsp_queue_idx, crsp_queue_data, req_uuid_st1));
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end
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if (mreq_queue_push) begin
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if (do_creq_wr_st1)
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`TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_byteen, mreq_queue_data, req_uuid_st1));
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`TRACE(2, ("%d: %s writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_byteen, mreq_queue_data, req_uuid_st1));
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else
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`TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_id, req_uuid_st1));
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`TRACE(2, ("%d: %s fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_id, req_uuid_st1));
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end
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end
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`endif
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40
hw/rtl/cache/VX_cache_data.sv
vendored
40
hw/rtl/cache/VX_cache_data.sv
vendored
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -17,11 +17,11 @@ module VX_cache_data #(
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parameter `STRING INSTANCE_ID= "",
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parameter BANK_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 16,
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parameter LINE_SIZE = 16,
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// Number of banks
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parameter NUM_BANKS = 1,
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parameter NUM_BANKS = 1,
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// Number of associative ways
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parameter NUM_WAYS = 1,
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// Size of a word in bytes
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@ -41,7 +41,7 @@ module VX_cache_data #(
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input wire stall,
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input wire read,
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input wire fill,
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input wire fill,
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input wire write,
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input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr,
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input wire [`UP(`CS_WORD_SEL_BITS)-1:0] wsel,
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@ -73,12 +73,12 @@ module VX_cache_data #(
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wren_r = '0;
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wren_r[wsel] = byteen;
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end
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// order the data layout to perform ways multiplexing last
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// order the data layout to perform ways multiplexing last
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// this allows performing onehot encoding of the way index in parallel with BRAM read.
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wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][WORD_SIZE-1:0] wren_w;
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for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin
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assign wdata[i] = fill ? {NUM_WAYS{fill_data[i]}} : {NUM_WAYS{wdata_r[i]}};
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assign wdata[i] = fill ? {NUM_WAYS{fill_data[i]}} : {NUM_WAYS{wdata_r[i]}};
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for (genvar j = 0; j < NUM_WAYS; ++j) begin
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assign wren_w[i][j] = (fill ? {WORD_SIZE{1'b1}} : wren_r[i])
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& {WORD_SIZE{((NUM_WAYS == 1) || way_sel[j])}};
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@ -92,7 +92,7 @@ module VX_cache_data #(
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assign wdata = fill_data;
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assign wren = fill;
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end
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wire [`LOG2UP(NUM_WAYS)-1:0] way_idx;
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VX_onehot_encoder #(
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@ -106,7 +106,7 @@ module VX_cache_data #(
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wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] rdata;
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wire [`CS_LINE_SEL_BITS-1:0] line_sel = line_addr[`CS_LINE_SEL_BITS-1:0];
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VX_sp_ram #(
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.DATAW (`CS_LINE_WIDTH * NUM_WAYS),
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.SIZE (`CS_LINES_PER_BANK),
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@ -119,7 +119,7 @@ module VX_cache_data #(
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.wren (wren),
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.addr (line_sel),
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.wdata (wdata),
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.rdata (rdata)
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.rdata (rdata)
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);
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wire [NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] per_way_rdata;
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@ -129,24 +129,24 @@ module VX_cache_data #(
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end else begin
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`UNUSED_VAR (wsel)
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assign per_way_rdata = rdata;
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end
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end
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assign read_data = per_way_rdata[way_idx];
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`UNUSED_VAR (stall)
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`ifdef DBG_TRACE_CACHE
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (fill && ~stall) begin
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`TRACE(3, ("%d: %s-bank%0d data-fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data));
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`TRACE(3, ("%d: %s fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data));
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end
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if (read && ~stall) begin
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`TRACE(3, ("%d: %s-bank%0d data-read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid));
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end
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`TRACE(3, ("%d: %s read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid));
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end
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if (write && ~stall) begin
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`TRACE(3, ("%d: %s-bank%0d data-write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid));
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end
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end
|
||||
`TRACE(3, ("%d: %s write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid));
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
18
hw/rtl/cache/VX_cache_mshr.sv
vendored
18
hw/rtl/cache/VX_cache_mshr.sv
vendored
|
@ -216,13 +216,13 @@ module VX_cache_mshr #(
|
|||
next_table <= next_table_n;
|
||||
end
|
||||
|
||||
`RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID,
|
||||
`RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, lkp_req_uuid))
|
||||
|
||||
`RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID,
|
||||
`RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid))
|
||||
|
||||
`RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, BANK_ID,
|
||||
`RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id))
|
||||
|
||||
VX_dp_ram #(
|
||||
|
@ -264,22 +264,22 @@ module VX_cache_mshr #(
|
|||
show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire;
|
||||
end
|
||||
if (allocate_fire)
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
|
||||
`TRACE(3, ("%d: %s allocate: addr=0x%0h, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_prev, allocate_id, lkp_req_uuid));
|
||||
if (lookup_valid)
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
|
||||
`TRACE(3, ("%d: %s lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_matches, lkp_req_uuid));
|
||||
if (finalize_valid)
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
|
||||
`TRACE(3, ("%d: %s finalize release=%b, pending=%b, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID,
|
||||
finalize_release, finalize_pending, finalize_prev, finalize_id, fin_req_uuid));
|
||||
if (fill_valid)
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, BANK_ID,
|
||||
`TRACE(3, ("%d: %s fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id));
|
||||
if (dequeue_fire)
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
|
||||
`TRACE(3, ("%d: %s dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID,
|
||||
`CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid));
|
||||
if (show_table) begin
|
||||
`TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INSTANCE_ID, BANK_ID));
|
||||
`TRACE(3, ("%d: %s table", $time, INSTANCE_ID));
|
||||
for (integer i = 0; i < MSHR_SIZE; ++i) begin
|
||||
if (valid_table[i]) begin
|
||||
`TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID)));
|
||||
|
|
38
hw/rtl/cache/VX_cache_tags.sv
vendored
38
hw/rtl/cache/VX_cache_tags.sv
vendored
|
@ -1,10 +1,10 @@
|
|||
// Copyright © 2019-2023
|
||||
//
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
|
@ -17,15 +17,15 @@ module VX_cache_tags #(
|
|||
parameter `STRING INSTANCE_ID = "",
|
||||
parameter BANK_ID = 0,
|
||||
// Size of cache in bytes
|
||||
parameter CACHE_SIZE = 1024,
|
||||
parameter CACHE_SIZE = 1024,
|
||||
// Size of line inside a bank in bytes
|
||||
parameter LINE_SIZE = 16,
|
||||
parameter LINE_SIZE = 16,
|
||||
// Number of banks
|
||||
parameter NUM_BANKS = 1,
|
||||
parameter NUM_BANKS = 1,
|
||||
// Number of associative ways
|
||||
parameter NUM_WAYS = 1,
|
||||
parameter NUM_WAYS = 1,
|
||||
// Size of a word in bytes
|
||||
parameter WORD_SIZE = 1,
|
||||
parameter WORD_SIZE = 1,
|
||||
// Request debug identifier
|
||||
parameter UUID_WIDTH = 0
|
||||
) (
|
||||
|
@ -41,7 +41,7 @@ module VX_cache_tags #(
|
|||
// read/fill
|
||||
input wire lookup,
|
||||
input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr,
|
||||
input wire fill,
|
||||
input wire fill,
|
||||
input wire init,
|
||||
output wire [NUM_WAYS-1:0] way_sel,
|
||||
output wire [NUM_WAYS-1:0] tag_matches
|
||||
|
@ -65,7 +65,7 @@ module VX_cache_tags #(
|
|||
end else if (~stall) begin // hold the value on stalls prevent filling different slots twice
|
||||
repl_way <= {repl_way[NUM_WAYS-2:0], repl_way[NUM_WAYS-1]};
|
||||
end
|
||||
end
|
||||
end
|
||||
for (genvar i = 0; i < NUM_WAYS; ++i) begin
|
||||
assign way_sel[i] = fill && repl_way[i];
|
||||
end
|
||||
|
@ -86,31 +86,31 @@ module VX_cache_tags #(
|
|||
.clk (clk),
|
||||
.read (1'b1),
|
||||
.write (way_sel[i] || init),
|
||||
`UNUSED_PIN (wren),
|
||||
`UNUSED_PIN (wren),
|
||||
.addr (line_sel),
|
||||
.wdata ({~init, line_tag}),
|
||||
.wdata ({~init, line_tag}),
|
||||
.rdata ({read_valid, read_tag})
|
||||
);
|
||||
|
||||
|
||||
assign tag_matches[i] = read_valid && (line_tag == read_tag);
|
||||
end
|
||||
|
||||
|
||||
`ifdef DBG_TRACE_CACHE
|
||||
always @(posedge clk) begin
|
||||
if (fill && ~stall) begin
|
||||
`TRACE(3, ("%d: %s-bank%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag));
|
||||
`TRACE(3, ("%d: %s fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag));
|
||||
end
|
||||
if (init) begin
|
||||
`TRACE(3, ("%d: %s-bank%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel));
|
||||
`TRACE(3, ("%d: %s init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel));
|
||||
end
|
||||
if (lookup && ~stall) begin
|
||||
if (tag_matches != 0) begin
|
||||
`TRACE(3, ("%d: %s-bank%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid));
|
||||
`TRACE(3, ("%d: %s hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid));
|
||||
end else begin
|
||||
`TRACE(3, ("%d: %s-bank%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid));
|
||||
`TRACE(3, ("%d: %s miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
|
@ -193,9 +193,9 @@ module VX_alu_int #(
|
|||
|
||||
`ifdef DBG_TRACE_PIPELINE
|
||||
always @(posedge clk) begin
|
||||
if (branch_ctl_if.valid) begin
|
||||
if (br_enable) begin
|
||||
`TRACE(1, ("%d: %s-branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n",
|
||||
$time, INSTANCE_ID, branch_ctl_if.wid, {commit_if.data.PC, 1'b0}, branch_ctl_if.taken, {branch_ctl_if.dest, 1'b0}, commit_if.data.uuid));
|
||||
$time, INSTANCE_ID, br_wid, {commit_if.data.PC, 1'b0}, br_taken, {br_dest, 1'b0}, commit_if.data.uuid));
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
|
|
@ -32,6 +32,7 @@ import VX_gpu_pkg::*;
|
|||
import VX_fpu_pkg::*;
|
||||
`endif
|
||||
#(
|
||||
parameter `STRING INSTANCE_ID = "",
|
||||
parameter CORE_ID = 0
|
||||
) (
|
||||
input wire clk,
|
||||
|
@ -146,7 +147,7 @@ import VX_fpu_pkg::*;
|
|||
mscratch <= write_data;
|
||||
end
|
||||
default: begin
|
||||
`ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
|
||||
`ASSERT(0, ("%t: *** %s invalid CSR write address: %0h (#%0d)", $time, INSTANCE_ID, write_addr, write_uuid));
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
|
|
@ -73,7 +73,8 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
|
|||
wire csr_write_enable = (execute_if.data.op_type == `INST_SFU_CSRRW);
|
||||
|
||||
VX_csr_data #(
|
||||
.CORE_ID (CORE_ID)
|
||||
.INSTANCE_ID (INSTANCE_ID),
|
||||
.CORE_ID (CORE_ID)
|
||||
) csr_data (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
|
|
@ -89,7 +89,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
|
|||
`endif
|
||||
|
||||
`RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0),
|
||||
("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, {schedule_if.data.PC, 1'b0}, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid))
|
||||
("%t: *** %s invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, INSTANCE_ID, {schedule_if.data.PC, 1'b0}, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid))
|
||||
|
||||
// Icache Request
|
||||
|
||||
|
|
|
@ -414,7 +414,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
|
|||
end
|
||||
end
|
||||
end
|
||||
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** %s-scheduler-timeout: stalled_warps=%b", $time, INSTANCE_ID, stalled_warps))
|
||||
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** %s timeout: stalled_warps=%b", $time, INSTANCE_ID, stalled_warps))
|
||||
|
||||
`ifdef PERF_ENABLE
|
||||
reg [`PERF_CTR_BITS-1:0] perf_sched_idles;
|
||||
|
|
|
@ -273,12 +273,12 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
|
|||
end
|
||||
|
||||
`RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
|
||||
("%t: *** %s-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
|
||||
("%t: *** %s timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
|
||||
$time, INSTANCE_ID, i, {staging_if[i].data.PC, 1'b0}, staging_if[i].data.tmask, timeout_ctr,
|
||||
operands_busy, staging_if[i].data.uuid));
|
||||
|
||||
`RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if.data.rd] != 0,
|
||||
("%t: *** %s: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
|
||||
("%t: *** %s invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
|
||||
$time, INSTANCE_ID, i, {writeback_if.data.PC, 1'b0}, writeback_if.data.tmask, writeback_if.data.rd, writeback_if.data.uuid));
|
||||
`endif
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue