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fixed degenerate writes to R0

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This commit is contained in:
Blaise Tine 2024-07-10 16:40:37 -07:00
parent 13d5a9c969
commit d6770f7adc
1 changed files with 7 additions and 2 deletions
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9
hw/rtl/core/VX_operands.sv
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@ -256,6 +256,11 @@ module VX_operands import VX_gpu_pkg::*; #(
assign gpr_wr_enabled = wr_enabled && writeback_if.valid;
end
wire [PER_BANK_ADDRW-1:0] gpr_wr_addr_b = gpr_wr_addr[BANK_SEL_BITS +: PER_BANK_ADDRW];
// prevent degenerate writes to R0
wire gpr_wr_enabled_qual = gpr_wr_enabled && (| gpr_wr_addr);
wire [BYTEENW-1:0] wren;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign wren[i*XLEN_SIZE+:XLEN_SIZE] = {XLEN_SIZE{writeback_if.data.tmask[i]}};
@ -272,8 +277,8 @@ module VX_operands import VX_gpu_pkg::*; #(
.clk (clk),
.read (1'b1),
.wren (wren),
.write (gpr_wr_enabled),
.waddr (gpr_wr_addr[BANK_SEL_BITS +: PER_BANK_ADDRW]),
.write (gpr_wr_enabled_qual),
.waddr (gpr_wr_addr_b),
.wdata (writeback_if.data.data),
.raddr (gpr_rd_addr[b]),
.rdata (gpr_rd_data[b])