fixed byteen signal on memory read

hw/rtl/VX_define.vh

@@ -361,7 +361,7 @@
     assign dst.req_data.rw = 0; \
     assign dst.req_data.addr = src.req_data.addr; \
     assign dst.req_data.data = '0; \
-    assign dst.req_data.byteen = '0; \
+    assign dst.req_data.byteen = '1; \
     assign dst.req_data.flags = src.req_data.flags; \
     assign dst.req_data.tag = src.req_data.tag; \
     assign src.req_ready = dst.req_ready; \

hw/rtl/cache/VX_cache_bank.sv

@@ -623,7 +623,7 @@ module VX_cache_bank #(
     end else begin
         assign mreq_queue_rw = 0;
         assign mreq_queue_data = '0;
-        assign mreq_queue_byteen = '0;
+        assign mreq_queue_byteen = '1;
         `UNUSED_VAR (dirty_data_st1)
         `UNUSED_VAR (dirty_byteen_st1)
     end

hw/rtl/cache/VX_cache_data.sv

@@ -101,7 +101,7 @@ module VX_cache_data #(
 
             assign dirty_byteen = bs_rdata[way_idx];
         end else begin
-            assign dirty_byteen = {LINE_SIZE{1'b1}};
+            assign dirty_byteen = '1;
         end
 
         wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] flipped_rdata;
@@ -112,7 +112,7 @@ module VX_cache_data #(
         end
         assign dirty_data = flipped_rdata[way_idx];
     end else begin
-        assign dirty_byteen = '0;
+        assign dirty_byteen = '1;
         assign dirty_data = '0;
     end
 

hw/rtl/core/VX_fetch.sv

@@ -118,7 +118,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
 
     assign icache_bus_if.req_data.flags  = '0;
     assign icache_bus_if.req_data.rw     = 0;
-    assign icache_bus_if.req_data.byteen = 4'b1111;
+    assign icache_bus_if.req_data.byteen = '1;
     assign icache_bus_if.req_data.data   = '0;
 
     // Icache Response