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minor update

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This commit is contained in:
Blaise Tine 2023-03-18 16:49:42 -04:00
parent 68f69b6c72
commit 2063eadf8c
4 changed files with 19 additions and 15 deletions
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4
hw/rtl/core/VX_csr_data.sv
View file

@ -120,8 +120,8 @@ module VX_csr_data #(
read_addr_valid_r = 1;
case (read_addr)
`ifdef EXT_F_ENABLE
`CSR_FFLAGS : read_data_rw_r = `XLEN'(fcsr[read_wid][`FFLAGS_BITS-1:0]);
`CSR_FRM : read_data_rw_r = `XLEN'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]);
`CSR_FFLAGS : read_data_rw_r = `XLEN'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
`CSR_FRM : read_data_rw_r = `XLEN'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
`CSR_FCSR : read_data_rw_r = `XLEN'(fcsr[read_wid]);
`endif
`CSR_LWID : read_data_ro_r = `XLEN'(read_wid);

2
hw/rtl/fpu_unit/VX_fpu_arb.sv
View file

@ -30,7 +30,7 @@ module VX_fpu_arb #(
localparam NUM_REQS = 1 << LOG_NUM_REQS;
localparam TAG_OUT_WIDTH = TAG_WIDTH + LOG_NUM_REQS;
localparam REQ_DATAW = TAG_OUT_WIDTH + `INST_FPU_BITS + `INST_FRM_BITS + NUM_LANES * 3 * `XLEN;
localparam RSP_DATAW = TAG_WIDTH + NUM_LANES * (`XLEN + `FFLAGS_BITS) + 1;
localparam RSP_DATAW = TAG_WIDTH + NUM_LANES * (`XLEN + `FP_FLAGS_BITS) + 1;
///////////////////////////////////////////////////////////////////////

16
hw/rtl/fpu_unit/VX_fpu_class.sv
View file

@ -7,7 +7,7 @@ module VX_fpu_class # (
) (
input [EXP_BITS-1:0] exp_i,
input [MAN_BITS-1:0] man_i,
output fclass_t clss_o
output fclass_t fclass_o
);
wire is_normal = (exp_i != '0) && (exp_i != '1);
wire is_zero = (exp_i == '0) && (man_i == '0);
@ -17,12 +17,12 @@ module VX_fpu_class # (
wire is_signaling = is_nan && ~man_i[MAN_BITS-1];
wire is_quiet = is_nan && ~is_signaling;
assign clss_o.is_normal = is_normal;
assign clss_o.is_zero = is_zero;
assign clss_o.is_subnormal = is_subnormal;
assign clss_o.is_inf = is_inf;
assign clss_o.is_nan = is_nan;
assign clss_o.is_quiet = is_quiet;
assign clss_o.is_signaling = is_signaling;
assign fclass_o.is_normal = is_normal;
assign fclass_o.is_zero = is_zero;
assign fclass_o.is_subnormal = is_subnormal;
assign fclass_o.is_inf = is_inf;
assign fclass_o.is_nan = is_nan;
assign fclass_o.is_quiet = is_quiet;
assign fclass_o.is_signaling = is_signaling;
endmodule

12
hw/rtl/fpu_unit/VX_fpu_ncomp.sv
View file

@ -173,7 +173,8 @@ module VX_fpu_ncomp #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
always @(*) begin
case (frm_s0)
`INST_FRM_RNE: begin // LE
`INST_FRM_RNE: begin // LE
fcmp_fflags[i] = 5'h0;
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags_NV[i] = 1'b1;
@ -183,6 +184,7 @@ module VX_fpu_ncomp #(
end
end
`INST_FRM_RTZ: begin // LS
fcmp_fflags[i] = 5'h0;
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags_NV[i] = 1'b1;
@ -192,9 +194,10 @@ module VX_fpu_ncomp #(
end
end
`INST_FRM_RDN: begin // EQ
fcmp_fflags[i] = 5'h0;
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags_NV[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
fcmp_fflags[i].NV = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
end else begin
fcmp_res[i] = {31'h0, ab_equal_s0[i]};
fcmp_fflags_NV[i] = 1'b0;
@ -233,7 +236,8 @@ module VX_fpu_ncomp #(
end
3,4: begin
tmp_result[i] = fminmax_res[i];
tmp_fflags_NV[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
tmp_fflags[i] = 0;
tmp_fflags[i].NV = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
end
//5,6,7: MOVE
default: begin
@ -256,7 +260,7 @@ module VX_fpu_ncomp #(
wire [NUM_LANES-1:0] fflags_NV;
VX_pipe_register #(
.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + (NUM_LANES * 1)),
.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + (NUM_LANES * `FP_FLAGS_BITS)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),