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minor update

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This commit is contained in:
Blaise Tine 2024-09-08 17:49:28 -07:00
parent b1dc2fba42
commit 207840a97e
2 changed files with 62 additions and 68 deletions
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122
hw/rtl/afu/opae/vortex_afu.sv
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@ -260,7 +260,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
mmio_rsp.data <= 64'({cout_q_dout_s, !cout_q_empty, 8'(state)});
`ifdef DBG_TRACE_AFU
if (state != STATE_WIDTH'(mmio_rsp.data)) begin
`TRACE(2, ("%d: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_req_hdr.address, state))
`TRACE(2, ("%d: AFU: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_req_hdr.address, state))
end
`endif
end
@ -268,28 +268,28 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
MMIO_SCOPE_READ: begin
mmio_rsp.data <= cmd_scope_rdata;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_SCOPE_READ: data=0x%h\n", $time, cmd_scope_rdata))
`TRACE(2, ("%d: AFU: MMIO_SCOPE_READ: data=0x%h\n", $time, cmd_scope_rdata))
`endif
end
`endif
MMIO_DEV_CAPS: begin
mmio_rsp.data <= dev_caps;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_DEV_CAPS: data=0x%h\n", $time, dev_caps))
`TRACE(2, ("%d: AFU: MMIO_DEV_CAPS: data=0x%h\n", $time, dev_caps))
`endif
end
MMIO_ISA_CAPS: begin
mmio_rsp.data <= isa_caps;
`ifdef DBG_TRACE_AFU
if (state != STATE_WIDTH'(mmio_rsp.data)) begin
`TRACE(2, ("%d: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps))
`TRACE(2, ("%d: AFU: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps))
end
`endif
end
default: begin
mmio_rsp.data <= 64'h0;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_req_hdr.address))
`TRACE(2, ("%d: AFU: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_req_hdr.address))
`endif
end
endcase
@ -303,30 +303,30 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
MMIO_CMD_ARG0: begin
cmd_args[0] <= 64'(cp2af_sRxPort.c0.data);
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_CMD_ARG0: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data)))
`TRACE(2, ("%d: AFU: MMIO_CMD_ARG0: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data)))
`endif
end
MMIO_CMD_ARG1: begin
cmd_args[1] <= 64'(cp2af_sRxPort.c0.data);
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_CMD_ARG1: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data)))
`TRACE(2, ("%d: AFU: MMIO_CMD_ARG1: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data)))
`endif
end
MMIO_CMD_ARG2: begin
cmd_args[2] <= 64'(cp2af_sRxPort.c0.data);
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_CMD_ARG2: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data)))
`TRACE(2, ("%d: AFU: MMIO_CMD_ARG2: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data)))
`endif
end
MMIO_CMD_TYPE: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_CMD_TYPE: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data)))
`TRACE(2, ("%d: AFU: MMIO_CMD_TYPE: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data)))
`endif
end
`ifdef SCOPE
MMIO_SCOPE_WRITE: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: MMIO_SCOPE_WRITE: data=0x%h\n", $time, cmd_scope_wdata))
`TRACE(2, ("%d: AFU: MMIO_SCOPE_WRITE: data=0x%h\n", $time, cmd_scope_wdata))
`endif
end
`endif
@ -344,18 +344,10 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
wire cmd_mem_rd_done;
reg cmd_mem_wr_done;
reg vx_busy_wait;
reg vx_running;
wire vx_busy;
reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
always @(posedge clk) begin
if (state == STATE_RUN) begin
vx_reset_ctr <= vx_reset_ctr + $bits(vx_reset_ctr)'(1);
end else begin
vx_reset_ctr <= '0;
end
end
reg vx_busy_wait;
reg vx_reset = 1; // asserted at initialization
wire vx_busy;
wire is_mmio_wr_cmd = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_req_hdr.address);
wire [CMD_TYPE_WIDTH-1:0] cmd_type = is_mmio_wr_cmd ?
@ -363,37 +355,37 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
always @(posedge clk) begin
if (reset) begin
state <= STATE_IDLE;
vx_busy_wait <= 0;
vx_running <= 0;
state <= STATE_IDLE;
vx_reset <= 1;
end else begin
case (state)
STATE_IDLE: begin
case (cmd_type)
CMD_MEM_READ: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE MEM_READ: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size))
`TRACE(2, ("%d: AFU: Goto STATE MEM_READ: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size))
`endif
state <= STATE_MEM_READ;
end
CMD_MEM_WRITE: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE MEM_WRITE: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size))
`TRACE(2, ("%d: AFU: Goto STATE MEM_WRITE: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size))
`endif
state <= STATE_MEM_WRITE;
end
CMD_DCR_WRITE: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE DCR_WRITE: addr=0x%0h data=%0d\n", $time, cmd_dcr_addr, cmd_dcr_data))
`TRACE(2, ("%d: AFU: Goto STATE DCR_WRITE: addr=0x%0h data=%0d\n", $time, cmd_dcr_addr, cmd_dcr_data))
`endif
state <= STATE_DCR_WRITE;
end
CMD_RUN: begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE RUN\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE RUN\n", $time))
`endif
state <= STATE_RUN;
vx_running <= 0;
vx_reset_ctr <= (`RESET_DELAY-1);
vx_reset <= 1;
end
default: begin
state <= state;
@ -404,54 +396,56 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
if (cmd_mem_rd_done) begin
state <= STATE_IDLE;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE IDLE\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE IDLE\n", $time))
`endif
end
end
STATE_MEM_WRITE: begin
if (cmd_mem_wr_done) begin
state <= STATE_IDLE;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE IDLE\n", $time))
`endif
end
end
STATE_DCR_WRITE: begin
state <= STATE_IDLE;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE IDLE\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE IDLE\n", $time))
`endif
end
STATE_RUN: begin
if (vx_running) begin
if (vx_busy_wait) begin
// wait until the gpu goes busy
if (vx_busy) begin
vx_busy_wait <= 0;
end
end else begin
// wait until the gpu is not busy
if (~vx_busy) begin
state <= STATE_IDLE;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: AFU: End execution\n", $time))
`TRACE(2, ("%d: STATE IDLE\n", $time))
`endif
end
end
if (vx_reset) begin
// wait until the reset network is ready
if (vx_reset_ctr == 0) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: AFU: Begin execution\n", $time))
`endif
vx_busy_wait <= 1;
vx_reset <= 0;
end
end else begin
// wait until the reset sequence is complete
if (vx_reset_ctr == (`RESET_DELAY-1)) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: AFU: Begin execution\n", $time))
`endif
vx_running <= 1;
vx_busy_wait <= 1;
end
if (vx_busy_wait) begin
// wait until processor goes busy
if (vx_busy) begin
vx_busy_wait <= 0;
end
end else begin
// wait until the processor is not busy
if (~vx_busy) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: AFU: End execution\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE IDLE\n", $time))
`endif
state <= STATE_IDLE;
end
end
end
end
default:;
endcase
// ensure reset network initialization
if (vx_reset_ctr != '0) begin
vx_reset_ctr <= vx_reset_ctr - 1;
end
end
end
@ -745,7 +739,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
cci_rd_req_addr <= cci_rd_req_addr + 1;
cci_rd_req_ctr <= cci_rd_req_ctr + $bits(cci_rd_req_ctr)'(1);
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: CCI Rd Req: addr=0x%0h, tag=0x%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads))
`TRACE(2, ("%d: AFU: CCI Rd Req: addr=0x%0h, tag=0x%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads))
`endif
end
@ -755,13 +749,13 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE);
end
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=0x%h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data))
`TRACE(2, ("%d: AFU: CCI Rd Rsp: idx=%0d, ctr=%0d, data=0x%h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data))
`endif
end
if (cci_rdq_pop) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads))
`TRACE(2, ("%d: AFU: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads))
`endif
end
@ -899,13 +893,13 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
cci_wr_req_done <= 1;
end
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: CCI Wr Req: addr=0x%0h, rem=%0d, pending=%0d, data=0x%h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data))
`TRACE(2, ("%d: AFU: CCI Wr Req: addr=0x%0h, rem=%0d, pending=%0d, data=0x%h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data))
`endif
end
if (cci_wr_rsp_fire) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes))
`TRACE(2, ("%d: AFU: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes))
`endif
end
end
@ -933,7 +927,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
`SCOPE_IO_BIND (1)
.clk (clk),
.reset (reset || ~vx_running),
.reset (vx_reset),
// Memory request
.mem_req_valid (vx_mem_req_valid),

8
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -126,17 +126,16 @@ module VX_afu_wrap #(
if (reset || ap_reset) begin
state <= STATE_IDLE;
vx_pending_writes <= '0;
vx_reset_ctr <= (`RESET_DELAY-1);
vx_reset <= 1;
end else begin
case (state)
STATE_IDLE: begin
if (ap_start) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE RUN\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE RUN\n", $time))
`endif
state <= STATE_RUN;
vx_reset_ctr <= 0;
vx_reset_ctr <= (`RESET_DELAY-1);
vx_reset <= 1;
end
end
@ -161,6 +160,7 @@ module VX_afu_wrap #(
if (~vx_busy) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: AFU: End execution\n", $time))
`TRACE(2, ("%d: AFU: Goto STATE IDLE\n", $time))
`endif
state <= STATE_IDLE;
end
@ -170,7 +170,7 @@ module VX_afu_wrap #(
endcase
// ensure reset network initialization
if (vx_reset_ctr != 0) begin
if (vx_reset_ctr != '0) begin
vx_reset_ctr <= vx_reset_ctr - 1;
end