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cache read byteenable bug fix

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This commit is contained in:
Blaise Tine 2024-09-08 17:47:17 -07:00
parent cc105eaea9
commit b1dc2fba42
1 changed files with 12 additions and 3 deletions
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15
hw/rtl/cache/VX_cache_bank.sv vendored
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@ -617,9 +617,18 @@ module VX_cache_bank #(
assign mreq_queue_flush = creq_flush_st1;
if (WRITE_ENABLE) begin
assign mreq_queue_rw = WRITEBACK ? is_fill_or_flush_st1 : rw_st1;
assign mreq_queue_data = WRITEBACK ? dirty_data_st1 : write_data_st1;
assign mreq_queue_byteen = WRITEBACK ? dirty_byteen_st1 : write_byteen_st1;
if (WRITEBACK) begin
assign mreq_queue_rw = is_fill_or_flush_st1;
assign mreq_queue_data = dirty_data_st1;
assign mreq_queue_byteen = is_fill_or_flush_st1 ? dirty_byteen_st1 : '1;
end else begin
assign mreq_queue_rw = rw_st1;
assign mreq_queue_data = write_data_st1;
assign mreq_queue_byteen = rw_st1 ? write_byteen_st1 : '1;
`UNUSED_VAR (is_fill_or_flush_st1)
`UNUSED_VAR (dirty_data_st1)
`UNUSED_VAR (dirty_byteen_st1)
end
end else begin
assign mreq_queue_rw = 0;
assign mreq_queue_data = '0;