merge

hw/rtl/VX_csr_data.v

@@ -78,7 +78,7 @@ module VX_csr_data (
 
     assign read_csr_data =  read_cycle    ? cycle[31:0] :
                                 read_cycleh   ? cycle[63:32] :
-                                read_instret  ? instret[31:0] :
-                                read_instreth ? instret[63:32] :
-                                                {{20{1'b0}}, csr[read_addr]};
+                                    read_instret  ? instret[31:0] :
+                                        read_instreth ? instret[63:32] :
+                                            {{20{1'b0}}, csr[read_addr]};
 endmodule : VX_csr_data

hw/rtl/VX_scheduler.v

@@ -50,7 +50,6 @@ module VX_scheduler (
     integer i, w;
     
     always @(posedge clk) begin
-
         if (reset) begin
             for (w = 0; w < `NUM_WARPS; w=w+1) begin
                 for (i = 0; i < 32; i = i + 1) begin

hw/rtl/cache/VX_cache_req_queue.v

@@ -173,7 +173,7 @@ module VX_cache_req_queue #(
 
     always @(posedge clk) begin
         if (reset) begin
-             use_per_valids   <= 0;
+            use_per_valids    <= 0;
             use_per_addr      <= 0;
             use_per_writedata <= 0;
             use_per_rd        <= 0;