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minor update
This commit is contained in:
Blaise Tine
parent
f63233334e
commit
26df675e24
1 changed files with 95 additions and 86 deletions
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@ -338,11 +338,22 @@ private:
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for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
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*m_axi_mem_[i].arready = 1;
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*m_axi_mem_[i].awready = 1;
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*m_axi_mem_[i].wready = 1;
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}
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}
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void tick() {
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this->axi_mem_bus_eval();
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device_->ap_clk = 0;
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this->eval();
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this->axi_mem_bus_eval(0);
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device_->ap_clk = 1;
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this->eval();
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this->axi_mem_bus_eval(1);
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dram_sim_.tick();
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for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
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if (!dram_queues_[i].empty()) {
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@ -360,13 +371,6 @@ private:
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}
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}
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dram_sim_.tick();
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device_->ap_clk = 0;
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this->eval();
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device_->ap_clk = 1;
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this->eval();
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#ifndef NDEBUG
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fflush(stdout);
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#endif
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@ -404,149 +408,154 @@ private:
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}
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void axi_mem_bus_reset() {
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for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
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for (int b = 0; b < PLATFORM_MEMORY_BANKS; ++b) {
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// read request address
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*m_axi_mem_[i].arready = 0;
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*m_axi_mem_[b].arready = 0;
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// write request address
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*m_axi_mem_[i].awready = 0;
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*m_axi_mem_[b].awready = 0;
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// write request data
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*m_axi_mem_[i].wready = 0;
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*m_axi_mem_[b].wready = 0;
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// read response
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*m_axi_mem_[i].rvalid = 0;
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*m_axi_mem_[b].rvalid = 0;
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// write response
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*m_axi_mem_[i].bvalid = 0;
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*m_axi_mem_[b].bvalid = 0;
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// states
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m_axi_states_[i].write_req_pending = false;
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m_axi_states_[i].write_rsp_pending = false;
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m_axi_states_[i].read_rsp_pending = false;
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m_axi_states_[b].write_req_addr_ack = false;
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m_axi_states_[b].write_req_data_ack = false;
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}
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}
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void axi_mem_bus_eval() {
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for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
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// handle read responses
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if (*m_axi_mem_[i].rvalid && (*m_axi_mem_[i].rready || ~m_axi_states_[i].read_rsp_pending)) {
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*m_axi_mem_[i].rvalid = 0;
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m_axi_states_[i].read_rsp_pending = false;
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void axi_mem_bus_eval(bool clk) {
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if (!clk) {
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for (int b = 0; b < PLATFORM_MEMORY_BANKS; ++b) {
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m_axi_states_[b].read_rsp_ready = *m_axi_mem_[b].rready;
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m_axi_states_[b].write_rsp_ready = *m_axi_mem_[b].bready;
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}
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if (!*m_axi_mem_[i].rvalid) {
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if (!pending_mem_reqs_[i].empty()
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&& (*pending_mem_reqs_[i].begin())->ready
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&& !(*pending_mem_reqs_[i].begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_[i].begin();
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return;
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}
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for (int b = 0; b < PLATFORM_MEMORY_BANKS; ++b) {
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// handle read responses
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if (*m_axi_mem_[b].rvalid && m_axi_states_[b].read_rsp_ready) {
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*m_axi_mem_[b].rvalid = 0;
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}
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if (!*m_axi_mem_[b].rvalid) {
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if (!pending_mem_reqs_[b].empty()
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&& (*pending_mem_reqs_[b].begin())->ready
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&& !(*pending_mem_reqs_[b].begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_[b].begin();
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auto mem_rsp = *mem_rsp_it;
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*m_axi_mem_[i].rvalid = 1;
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*m_axi_mem_[i].rid = mem_rsp->tag;
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*m_axi_mem_[i].rresp = 0;
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*m_axi_mem_[i].rlast = 1;
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memcpy(m_axi_mem_[i].rdata->data(), mem_rsp->data.data(), PLATFORM_MEMORY_DATA_SIZE);
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pending_mem_reqs_[i].erase(mem_rsp_it);
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m_axi_states_[i].read_rsp_pending = !*m_axi_mem_[i].rready;
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*m_axi_mem_[b].rvalid = 1;
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*m_axi_mem_[b].rid = mem_rsp->tag;
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*m_axi_mem_[b].rresp = 0;
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*m_axi_mem_[b].rlast = 1;
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memcpy(m_axi_mem_[b].rdata->data(), mem_rsp->data.data(), PLATFORM_MEMORY_DATA_SIZE);
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pending_mem_reqs_[b].erase(mem_rsp_it);
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delete mem_rsp;
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}
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}
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// handle write responses
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if (*m_axi_mem_[i].bvalid && (*m_axi_mem_[i].bready || ~m_axi_states_[i].write_rsp_pending)) {
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*m_axi_mem_[i].bvalid = 0;
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m_axi_states_[i].write_rsp_pending = false;
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if (*m_axi_mem_[b].bvalid && m_axi_states_[b].write_rsp_ready) {
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*m_axi_mem_[b].bvalid = 0;
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}
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if (!*m_axi_mem_[i].bvalid) {
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if (!pending_mem_reqs_[i].empty()
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&& (*pending_mem_reqs_[i].begin())->ready
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&& (*pending_mem_reqs_[i].begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_[i].begin();
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if (!*m_axi_mem_[b].bvalid) {
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if (!pending_mem_reqs_[b].empty()
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&& (*pending_mem_reqs_[b].begin())->ready
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&& (*pending_mem_reqs_[b].begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_[b].begin();
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auto mem_rsp = *mem_rsp_it;
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*m_axi_mem_[i].bvalid = 1;
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*m_axi_mem_[i].bid = mem_rsp->tag;
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*m_axi_mem_[i].bresp = 0;
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pending_mem_reqs_[i].erase(mem_rsp_it);
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m_axi_states_[i].write_rsp_pending = !*m_axi_mem_[i].bready;
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*m_axi_mem_[b].bvalid = 1;
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*m_axi_mem_[b].bid = mem_rsp->tag;
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*m_axi_mem_[b].bresp = 0;
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pending_mem_reqs_[b].erase(mem_rsp_it);
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delete mem_rsp;
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}
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}
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// handle read requests
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if (*m_axi_mem_[i].arvalid && *m_axi_mem_[i].arready) {
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if (*m_axi_mem_[b].arvalid && *m_axi_mem_[b].arready) {
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auto mem_req = new mem_req_t();
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mem_req->tag = *m_axi_mem_[i].arid;
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mem_req->addr = uint64_t(*m_axi_mem_[i].araddr);
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mem_req->tag = *m_axi_mem_[b].arid;
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mem_req->addr = uint64_t(*m_axi_mem_[b].araddr);
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ram_->read(mem_req->data.data(), mem_req->addr, PLATFORM_MEMORY_DATA_SIZE);
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mem_req->write = false;
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mem_req->ready = false;
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pending_mem_reqs_[i].emplace_back(mem_req);
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pending_mem_reqs_[b].emplace_back(mem_req);
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/*printf("%0ld: [sim] axi-mem-read: bank=%d, addr=0x%lx, tag=0x%x, data=0x", timestamp, i, mem_req->addr, mem_req->tag);
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/*printf("%0ld: [sim] axi-mem-read: bank=%d, addr=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, mem_req->tag);
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for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
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printf("%02x", mem_req->data[i]);
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printf("%02x", mem_req->data[b]);
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}
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printf("\n");*/
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// send dram request
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dram_queues_[i].push(mem_req);
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dram_queues_[b].push(mem_req);
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}
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if (*m_axi_mem_[i].wready && !m_axi_states_[i].write_req_pending) {
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*m_axi_mem_[i].wready = 0;
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// handle write address requests
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if (*m_axi_mem_[b].awvalid && *m_axi_mem_[b].awready && !m_axi_states_[b].write_req_addr_ack) {
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m_axi_states_[b].write_req_addr = *m_axi_mem_[b].awaddr;
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m_axi_states_[b].write_req_tag = *m_axi_mem_[b].awid;
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m_axi_states_[b].write_req_addr_ack = true;
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}
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// handle address write requestsls
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if (*m_axi_mem_[i].awvalid && *m_axi_mem_[i].awready && !*m_axi_mem_[i].wready) {
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m_axi_states_[i].write_req_addr = *m_axi_mem_[i].awaddr;
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m_axi_states_[i].write_req_tag = *m_axi_mem_[i].awid;
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// activate data channel
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*m_axi_mem_[i].wready = 1;
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m_axi_states_[i].write_req_pending = !*m_axi_mem_[i].wvalid;
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// handle write data requests
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if (*m_axi_mem_[b].wvalid && *m_axi_mem_[b].wready && !m_axi_states_[b].write_req_data_ack) {
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m_axi_states_[b].write_req_byteen = *m_axi_mem_[b].wstrb;
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auto data = (const uint8_t*)m_axi_mem_[b].wdata->data();
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for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
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m_axi_states_[b].write_req_data[i] = data[i];
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}
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m_axi_states_[b].write_req_data_ack = true;
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}
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// handle data write requests
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if (*m_axi_mem_[i].wvalid && *m_axi_mem_[i].wready) {
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auto byteen = *m_axi_mem_[i].wstrb;
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auto data = (uint8_t*)m_axi_mem_[i].wdata->data();
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auto byte_addr = m_axi_states_[i].write_req_addr;
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for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; i++) {
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// handle write requests
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if (m_axi_states_[b].write_req_addr_ack && m_axi_states_[b].write_req_data_ack) {
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auto byteen = m_axi_states_[b].write_req_byteen;
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auto byte_addr = m_axi_states_[b].write_req_addr;
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for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[byte_addr + i] = data[i];
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(*ram_)[byte_addr + i] = m_axi_states_[b].write_req_data[i];
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}
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}
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auto mem_req = new mem_req_t();
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mem_req->tag = m_axi_states_[i].write_req_tag;
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mem_req->tag = m_axi_states_[b].write_req_tag;
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mem_req->addr = byte_addr;
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mem_req->write = true;
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mem_req->ready = false;
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pending_mem_reqs_[i].emplace_back(mem_req);
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pending_mem_reqs_[b].emplace_back(mem_req);
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/*printf("%0ld: [sim] axi-mem-write: bank=%d, addr=0x%lx, byteen=0x%lx, tag=0x%x, data=0x", timestamp, i, mem_req->addr, byteen, mem_req->tag);
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/*printf("%0ld: [sim] axi-mem-write: bank=%d, addr=0x%lx, byteen=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, byteen, mem_req->tag);
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for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
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printf("%02x", data[i]);
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printf("%02x", m_axi_states_[b].write_req_data[i]]);
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}
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printf("\n");*/
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// send dram request
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dram_queues_[i].push(mem_req);
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dram_queues_[b].push(mem_req);
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// deactivate data channel
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if (m_axi_states_[i].write_req_pending) {
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*m_axi_mem_[i].wready = 0;
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m_axi_states_[i].write_req_pending = false;
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}
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// clear acks
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m_axi_states_[b].write_req_addr_ack = false;
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m_axi_states_[b].write_req_data_ack = false;
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}
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}
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}
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typedef struct {
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std::array<uint8_t, PLATFORM_MEMORY_DATA_SIZE> write_req_data;
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uint64_t write_req_byteen;
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uint64_t write_req_addr;
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uint32_t write_req_tag;
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bool write_req_pending;
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bool write_rsp_pending;
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bool read_rsp_pending;
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bool read_rsp_ready;
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bool write_rsp_ready;
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bool write_req_addr_ack;
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bool write_req_data_ack;
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} m_axi_state_t;
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typedef struct {
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