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minor updates

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This commit is contained in:
Blaise Tine 2024-08-18 18:56:17 -07:00
parent 8e9026524a
commit 2762bd53ff
4 changed files with 8 additions and 4 deletions
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2
hw/rtl/core/VX_mem_unit.sv
View file

@ -205,7 +205,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.ARBITER ("P"), .ARBITER ("P"),
.REQ_OUT_BUF (0), .REQ_OUT_BUF (0),
.RSP_OUT_BUF (0) .RSP_OUT_BUF (0)
) lsu_adapter ( ) dcache_adapter (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.lsu_mem_if (dcache_coalesced_if), .lsu_mem_if (dcache_coalesced_if),

4
hw/rtl/core/VX_mem_unit_top.sv
View file

@ -24,6 +24,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
// LSU memory request // LSU memory request
input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_valid, input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_valid,
input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_rw, input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_rw,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0] lsu_req_mask,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_SIZE-1:0] lsu_req_byteen, input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_SIZE-1:0] lsu_req_byteen,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_ADDR_WIDTH-1:0] lsu_req_addr, input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_ADDR_WIDTH-1:0] lsu_req_addr,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][`MEM_REQ_FLAGS_WIDTH-1:0] lsu_req_flags, input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][`MEM_REQ_FLAGS_WIDTH-1:0] lsu_req_flags,
@ -33,6 +34,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
// LSU memory response // LSU memory response
output wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_valid, output wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_valid,
output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0] lsu_rsp_mask,
output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_rsp_data, output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_rsp_data,
output wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_rsp_tag, output wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_rsp_tag,
input wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_ready, input wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_ready,
@ -63,6 +65,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
assign lsu_mem_if[i].req_valid = lsu_req_valid[i]; assign lsu_mem_if[i].req_valid = lsu_req_valid[i];
assign lsu_mem_if[i].req_data.rw = lsu_req_rw[i]; assign lsu_mem_if[i].req_data.rw = lsu_req_rw[i];
assign lsu_mem_if[i].req_data.mask = lsu_req_mask[i];
assign lsu_mem_if[i].req_data.byteen = lsu_req_byteen[i]; assign lsu_mem_if[i].req_data.byteen = lsu_req_byteen[i];
assign lsu_mem_if[i].req_data.addr = lsu_req_addr[i]; assign lsu_mem_if[i].req_data.addr = lsu_req_addr[i];
assign lsu_mem_if[i].req_data.flags = lsu_req_flags[i]; assign lsu_mem_if[i].req_data.flags = lsu_req_flags[i];
@ -74,6 +77,7 @@ module VX_mem_unit_top import VX_gpu_pkg::*; #(
// LSU memory response // LSU memory response
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
assign lsu_rsp_valid[i] = lsu_mem_if[i].rsp_valid; assign lsu_rsp_valid[i] = lsu_mem_if[i].rsp_valid;
assign lsu_rsp_mask[i] = lsu_mem_if[i].rsp_data.mask;
assign lsu_rsp_data[i] = lsu_mem_if[i].rsp_data.data; assign lsu_rsp_data[i] = lsu_mem_if[i].rsp_data.data;
assign lsu_rsp_tag[i] = lsu_mem_if[i].rsp_data.tag; assign lsu_rsp_tag[i] = lsu_mem_if[i].rsp_data.tag;
assign lsu_mem_if[i].rsp_ready = lsu_rsp_ready[i]; assign lsu_mem_if[i].rsp_ready = lsu_rsp_ready[i];

4
hw/syn/altera/quartus/mem_unit/Makefile
View file

@ -1,7 +1,7 @@
PROJECT = VX_mem_init_top PROJECT = VX_mem_unit_top
TOP_LEVEL_ENTITY = $(PROJECT) TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv SRC_FILE = $(PROJECT).sv
include ../../common.mk include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core -I$(RTL_DIR)/fpu

2
hw/unittest/mem_unit_top/Makefile
View file

@ -19,7 +19,7 @@ DBG_TRACE_FLAGS :=
RTL_PKGS := $(RTL_DIR)/VX_gpu_pkg.sv RTL_PKGS := $(RTL_DIR)/VX_gpu_pkg.sv
RTL_INCLUDE := -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs RTL_INCLUDE := -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs
RTL_INCLUDE += -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core RTL_INCLUDE += -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core -I$(RTL_DIR)/fpu
TOP := VX_mem_unit_top TOP := VX_mem_unit_top