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synthesis of the memory unit and local memory

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This commit is contained in:
Blaise Tine 2024-08-18 16:03:59 -07:00
parent 3612ceda80
commit 8e9026524a
9 changed files with 302 additions and 6 deletions
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123
hw/rtl/core/VX_mem_unit_top.sv Normal file
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@ -0,0 +1,123 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
module VX_mem_unit_top import VX_gpu_pkg::*; #(
parameter `STRING INSTANCE_ID = "",
parameter LSU_WORD_WIDTH = LSU_WORD_SIZE * 8
) (
// Clock
input wire clk,
input wire reset,
// LSU memory request
input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_valid,
input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_rw,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_SIZE-1:0] lsu_req_byteen,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_ADDR_WIDTH-1:0] lsu_req_addr,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][`MEM_REQ_FLAGS_WIDTH-1:0] lsu_req_flags,
input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_req_data,
input wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_req_tag,
output wire [`NUM_LSU_BLOCKS-1:0] lsu_req_ready,
// LSU memory response
output wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_valid,
output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_rsp_data,
output wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_rsp_tag,
input wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_ready,
// Memory request
output wire [DCACHE_NUM_REQS-1:0] mem_req_valid,
output wire [DCACHE_NUM_REQS-1:0] mem_req_rw,
output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen,
output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] mem_req_addr,
output wire [DCACHE_NUM_REQS-1:0][`MEM_REQ_FLAGS_WIDTH-1:0] mem_req_flags,
output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] mem_req_data,
output wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] mem_req_tag,
input wire [DCACHE_NUM_REQS-1:0] mem_req_ready,
// Memory response
input wire [DCACHE_NUM_REQS-1:0] mem_rsp_valid,
input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] mem_rsp_data,
input wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] mem_rsp_tag,
output wire [DCACHE_NUM_REQS-1:0] mem_rsp_ready
);
VX_lsu_mem_if #(
.NUM_LANES (`NUM_LSU_LANES),
.DATA_SIZE (LSU_WORD_SIZE),
.TAG_WIDTH (LSU_TAG_WIDTH)
) lsu_mem_if[`NUM_LSU_BLOCKS]();
// LSU memory request
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
assign lsu_mem_if[i].req_valid = lsu_req_valid[i];
assign lsu_mem_if[i].req_data.rw = lsu_req_rw[i];
assign lsu_mem_if[i].req_data.byteen = lsu_req_byteen[i];
assign lsu_mem_if[i].req_data.addr = lsu_req_addr[i];
assign lsu_mem_if[i].req_data.flags = lsu_req_flags[i];
assign lsu_mem_if[i].req_data.data = lsu_req_data[i];
assign lsu_mem_if[i].req_data.tag = lsu_req_tag[i];
assign lsu_req_ready[i] = lsu_mem_if[i].req_ready;
end
// LSU memory response
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin
assign lsu_rsp_valid[i] = lsu_mem_if[i].rsp_valid;
assign lsu_rsp_data[i] = lsu_mem_if[i].rsp_data.data;
assign lsu_rsp_tag[i] = lsu_mem_if[i].rsp_data.tag;
assign lsu_mem_if[i].rsp_ready = lsu_rsp_ready[i];
end
VX_mem_bus_if #(
.DATA_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) mem_bus_if[DCACHE_NUM_REQS]();
// memory request
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
assign mem_req_valid[i] = mem_bus_if[i].req_valid;
assign mem_req_rw[i] = mem_bus_if[i].req_data.rw;
assign mem_req_byteen[i] = mem_bus_if[i].req_data.byteen;
assign mem_req_addr[i] = mem_bus_if[i].req_data.addr;
assign mem_req_flags[i] = mem_bus_if[i].req_data.flags;
assign mem_req_data[i] = mem_bus_if[i].req_data.data;
assign mem_req_tag[i] = mem_bus_if[i].req_data.tag;
assign mem_bus_if[i].req_ready = mem_req_ready[i];
end
// memory response
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
assign mem_bus_if[i].rsp_valid = mem_rsp_valid[i];
assign mem_bus_if[i].rsp_data.tag = mem_rsp_tag[i];
assign mem_bus_if[i].rsp_data.data = mem_rsp_data[i];
assign mem_rsp_ready[i] = mem_bus_if[i].rsp_ready;
end
`ifdef PERF_ENABLE
cache_perf_t lmem_perf = '0;
`endif
VX_mem_unit #(
.INSTANCE_ID (INSTANCE_ID)
) mem_unit (
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.lmem_perf (lmem_perf),
`endif
.lsu_mem_in_if (lsu_mem_if),
.dcache_bus_if (mem_bus_if)
);
endmodule

13
hw/rtl/mem/VX_local_mem_top.sv
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@ -24,8 +24,6 @@ module VX_local_mem_top import VX_gpu_pkg::*; #(
// Number of banks
parameter NUM_BANKS = 4,
// Address width
parameter ADDR_WIDTH = `CLOG2(SIZE),
// Size of a word in bytes
parameter WORD_SIZE = `XLEN/8,
@ -33,7 +31,13 @@ module VX_local_mem_top import VX_gpu_pkg::*; #(
parameter UUID_WIDTH = 0,
// Request tag size
parameter TAG_WIDTH = 16
parameter TAG_WIDTH = 16,
// Address width
parameter NUM_WORDS = SIZE / WORD_SIZE,
parameter WORDS_PER_BANK = NUM_WORDS / NUM_BANKS,
parameter BANK_ADDR_WIDTH = `CLOG2(WORDS_PER_BANK),
parameter ADDR_WIDTH = BANK_ADDR_WIDTH + `CLOG2(NUM_BANKS)
) (
input wire clk,
input wire reset,
@ -56,7 +60,8 @@ module VX_local_mem_top import VX_gpu_pkg::*; #(
);
VX_mem_bus_if #(
.DATA_SIZE (WORD_SIZE),
.TAG_WIDTH (TAG_WIDTH)
.TAG_WIDTH (TAG_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) mem_bus_if[NUM_REQS]();
// memory request

7
hw/syn/altera/quartus/Makefile
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@ -9,7 +9,7 @@ SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
.PHONY: dogfood unittest pipeline lmem cache fpu core issue vortex top test
.PHONY: dogfood unittest pipeline mem_unit lmem cache fpu core issue vortex top test
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log:
@ -30,6 +30,11 @@ pipeline:
cp pipeline/Makefile pipeline/$(BUILD_DIR)
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
mem_unit:
mkdir -p mem_unit/$(BUILD_DIR)
cp mem_unit/Makefile mem_unit/$(BUILD_DIR)
$(MAKE) -C mem_unit/$(BUILD_DIR) clean && $(MAKE) -C mem_unit/$(BUILD_DIR) > mem_unit/$(BUILD_DIR)/build.log 2>&1 &
lmem:
mkdir -p lmem/$(BUILD_DIR)
cp lmem/Makefile lmem/$(BUILD_DIR)

7
hw/syn/altera/quartus/mem_unit/Makefile Executable file
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@ -0,0 +1,7 @@
PROJECT = VX_mem_init_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core

8
hw/unittest/Makefile
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@ -5,6 +5,8 @@ all:
$(MAKE) -C cache_top
$(MAKE) -C core_top
$(MAKE) -C issue_top
$(MAKE) -C local_mem_top
$(MAKE) -C mem_unit_top
run:
$(MAKE) -C cache run
@ -13,6 +15,8 @@ run:
$(MAKE) -C cache_top run
$(MAKE) -C core_top run
$(MAKE) -C issue_top run
$(MAKE) -C local_mem_top run
$(MAKE) -C mem_unit_top run
clean:
$(MAKE) -C cache clean
@ -20,4 +24,6 @@ clean:
$(MAKE) -C mem_streamer clean
$(MAKE) -C cache_top clean
$(MAKE) -C core_top clean
$(MAKE) -C issue_top clean
$(MAKE) -C issue_top clean
$(MAKE) -C local_mem_top clean
$(MAKE) -C mem_unit_top clean

26
hw/unittest/local_mem_top/Makefile Normal file
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@ -0,0 +1,26 @@
ROOT_DIR := $(realpath ../../..)
include $(ROOT_DIR)/config.mk
PROJECT := local_mem_top
RTL_DIR := $(VORTEX_HOME)/hw/rtl
DPI_DIR := $(VORTEX_HOME)/hw/dpi
SRC_DIR := $(VORTEX_HOME)/hw/unittest/$(PROJECT)
CXXFLAGS := -I$(SRC_DIR) -I$(VORTEX_HOME)/hw/unittest/common -I$(VORTEX_HOME)/sim/common
CXXFLAGS += -I$(ROOT_DIR)/hw
SRCS := $(DPI_DIR)/util_dpi.cpp
SRCS += $(SRC_DIR)/main.cpp
DBG_TRACE_FLAGS :=
RTL_PKGS := $(RTL_DIR)/VX_gpu_pkg.sv
RTL_INCLUDE := -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs
RTL_INCLUDE += -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem
TOP := VX_local_mem_top
include ../common.mk

49
hw/unittest/local_mem_top/main.cpp Normal file
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@ -0,0 +1,49 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "vl_simulator.h"
#ifndef TRACE_START_TIME
#define TRACE_START_TIME 0ull
#endif
#ifndef TRACE_STOP_TIME
#define TRACE_STOP_TIME -1ull
#endif
static uint64_t timestamp = 0;
static bool trace_enabled = false;
static uint64_t trace_start_time = TRACE_START_TIME;
static uint64_t trace_stop_time = TRACE_STOP_TIME;
double sc_time_stamp() {
return timestamp;
}
bool sim_trace_enabled() {
if (timestamp >= trace_start_time
&& timestamp < trace_stop_time)
return true;
return trace_enabled;
}
void sim_trace_enable(bool enable) {
trace_enabled = enable;
}
int main(int argc, char **argv) {
// Initialize Verilators variables
Verilated::commandArgs(argc, argv);
return 0;
}

26
hw/unittest/mem_unit_top/Makefile Normal file
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@ -0,0 +1,26 @@
ROOT_DIR := $(realpath ../../..)
include $(ROOT_DIR)/config.mk
PROJECT := mem_unit_top
RTL_DIR := $(VORTEX_HOME)/hw/rtl
DPI_DIR := $(VORTEX_HOME)/hw/dpi
SRC_DIR := $(VORTEX_HOME)/hw/unittest/$(PROJECT)
CXXFLAGS := -I$(SRC_DIR) -I$(VORTEX_HOME)/hw/unittest/common -I$(VORTEX_HOME)/sim/common
CXXFLAGS += -I$(ROOT_DIR)/hw
SRCS := $(DPI_DIR)/util_dpi.cpp
SRCS += $(SRC_DIR)/main.cpp
DBG_TRACE_FLAGS :=
RTL_PKGS := $(RTL_DIR)/VX_gpu_pkg.sv
RTL_INCLUDE := -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs
RTL_INCLUDE += -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core
TOP := VX_mem_unit_top
include ../common.mk

49
hw/unittest/mem_unit_top/main.cpp Normal file
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@ -0,0 +1,49 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "vl_simulator.h"
#ifndef TRACE_START_TIME
#define TRACE_START_TIME 0ull
#endif
#ifndef TRACE_STOP_TIME
#define TRACE_STOP_TIME -1ull
#endif
static uint64_t timestamp = 0;
static bool trace_enabled = false;
static uint64_t trace_start_time = TRACE_START_TIME;
static uint64_t trace_stop_time = TRACE_STOP_TIME;
double sc_time_stamp() {
return timestamp;
}
bool sim_trace_enabled() {
if (timestamp >= trace_start_time
&& timestamp < trace_stop_time)
return true;
return trace_enabled;
}
void sim_trace_enable(bool enable) {
trace_enabled = enable;
}
int main(int argc, char **argv) {
// Initialize Verilators variables
Verilated::commandArgs(argc, argv);
return 0;
}