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minor update

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This commit is contained in:
Blaise Tine 2023-06-27 17:10:19 -04:00
parent 64e4481d82
commit 29deaf9012
7 changed files with 32 additions and 45 deletions
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2
hw/rtl/cache/VX_cache.sv vendored
View file

@ -150,7 +150,7 @@ module VX_cache #(
// Memory response buffering
wire mem_rsp_valid_s;
wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_s;
wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_s;
wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_s;
wire mem_rsp_ready_s;

33
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -156,8 +156,7 @@ module VX_cache_bank #(
wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1;
wire req_valid, valid_st0, valid_st1;
wire is_fill_st0, is_fill_st1;
wire is_mshr_st0, is_mshr_st1;
wire is_hit_st0, is_hit_st1;
wire is_mshr_st0, is_mshr_st1;
wire is_init_st0;
wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id_st0;
wire mshr_pending_st0, mshr_pending_st1;
@ -250,16 +249,12 @@ module VX_cache_bank #(
end
wire do_read_st0 = valid_st0 && is_read_st0;
wire do_mshr_st0 = valid_st0 && is_mshr_st0;
wire do_fill_st0 = valid_st0 && is_fill_st0;
wire do_init_st0 = valid_st0 && is_init_st0;
wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_init_st0);
wire tag_match_st0;
// added for associativity
wire [NUM_WAYS-1:0] way_sel_st0;
wire [NUM_WAYS-1:0] way_sel_st1;
wire [NUM_WAYS-1:0] tag_matches_st0, tag_matches_st1;
wire [NUM_WAYS-1:0] way_sel_st0, way_sel_st1;
VX_cache_tags #(
.INSTANCE_ID(INSTANCE_ID),
@ -284,28 +279,25 @@ module VX_cache_bank #(
.fill (do_fill_st0),
.init (do_init_st0),
.way_sel (way_sel_st0),
.tag_match (tag_match_st0)
.tag_matches(tag_matches_st0)
);
// we have a tag match
assign is_hit_st0 = tag_match_st0;
// ensure mshr replay always get a hit
`RUNTIME_ASSERT (~do_mshr_st0 || is_hit_st0, ("runtime error: invalid mshr replay"));
wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = is_read_st0 ? mshr_alloc_id_st0 : mshr_id_st0;
VX_pipe_register #(
.DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + 1 + NUM_WAYS + 1),
.DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + 1 + TAG_WIDTH) + MSHR_ADDR_WIDTH + NUM_WAYS + NUM_WAYS + 1),
.RESETW (1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.enable (~pipe_stall),
.data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_a_st0, is_hit_st0, way_sel_st0, mshr_pending_st0}),
.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, is_hit_st1, way_sel_st1, mshr_pending_st1})
.data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_a_st0, tag_matches_st0, way_sel_st0, mshr_pending_st0}),
.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, tag_matches_st1, way_sel_st1, mshr_pending_st1})
);
// we have a tag match
wire is_hit_st1 = | tag_matches_st1;
if (UUID_WIDTH != 0) begin
assign req_uuid_st1 = tag_st1[0][TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
@ -325,6 +317,9 @@ module VX_cache_bank #(
`UNUSED_VAR (do_write_miss_st1)
// ensure mshr replay always get a hit
`RUNTIME_ASSERT (~do_mshr_st1 || is_hit_st1, ("runtime error: invalid mshr replay"));
// detect BRAM's read-during-write hazard
assign rdw_hazard_st0 = do_fill_st0; // after a fill
always @(posedge clk) begin
@ -357,7 +352,7 @@ module VX_cache_bank #(
.read (do_read_hit_st1 || do_mshr_st1),
.fill (do_fill_st1),
.write (do_write_hit_st1),
.way_sel (way_sel_st1),
.way_sel (way_sel_st1 | tag_matches_st1),
.addr (addr_st1),
.wsel (wsel_st1),
.pmask (pmask_st1),

2
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -195,7 +195,7 @@ module VX_cache_cluster_top #(
// Number of ports per banks
parameter NUM_PORTS = 1,
// Number of associative ways
parameter NUM_WAYS = 2,
parameter NUM_WAYS = 4,
// Size of a word in bytes
parameter WORD_SIZE = 4,

18
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -31,7 +31,7 @@ module VX_cache_tags #(
input wire fill,
input wire init,
output wire [NUM_WAYS-1:0] way_sel,
output wire tag_match
output wire [NUM_WAYS-1:0] tag_matches
);
`UNUSED_SPARAM (INSTANCE_ID)
`UNUSED_PARAM (BANK_ID)
@ -40,10 +40,8 @@ module VX_cache_tags #(
localparam TAG_WIDTH = 1 + `CS_TAG_SEL_BITS;
wire [NUM_WAYS-1:0] tag_matches;
wire [`CS_LINE_SEL_BITS-1:0] line_addr = addr[`CS_LINE_SEL_BITS-1:0];
wire [`CS_TAG_SEL_BITS-1:0] line_tag = `CS_LINE_TAG_ADDR(addr);
wire [NUM_WAYS-1:0] fill_way;
wire [`CS_TAG_SEL_BITS-1:0] line_tag = `CS_LINE_TAG_ADDR(addr);
if (NUM_WAYS > 1) begin
reg [NUM_WAYS-1:0] repl_way;
@ -56,11 +54,11 @@ module VX_cache_tags #(
end
end
for (genvar i = 0; i < NUM_WAYS; ++i) begin
assign fill_way[i] = fill && repl_way[i];
assign way_sel[i] = fill && repl_way[i];
end
end else begin
`UNUSED_VAR (stall)
assign fill_way = fill;
assign way_sel = fill;
end
for (genvar i = 0; i < NUM_WAYS; ++i) begin
@ -73,7 +71,7 @@ module VX_cache_tags #(
.NO_RWCHECK (1)
) tag_store (
.clk (clk),
.write (fill_way[i] || init),
.write (way_sel[i] || init),
`UNUSED_PIN (wren),
.addr (line_addr),
.wdata ({~init, line_tag}),
@ -82,12 +80,6 @@ module VX_cache_tags #(
assign tag_matches[i] = read_valid && (line_tag == read_tag);
end
// found a tag match?
assign tag_match = (| tag_matches);
// return the selected way
assign way_sel = fill_way | tag_matches;
`ifdef DBG_TRACE_CACHE_TAG
always @(posedge clk) begin

16
hw/rtl/libs/VX_dp_ram.sv
View file

@ -242,14 +242,17 @@ module VX_dp_ram #(
// RAM emulation
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
wire [DATAW-1:0] ram_n;
for (genvar i = 0; i < WRENW; ++i) begin
assign ram_n[i * WSELW +: WSELW] = ((WRENW == 1) | wren[i]) ? wdata[i * WSELW +: WSELW] : ram[waddr][i * WSELW +: WSELW];
end
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if ((WRENW == 1) || wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
ram[waddr] <= ram_n;
end
rdata_r <= ram[raddr];
end
@ -260,10 +263,7 @@ module VX_dp_ram #(
reg prev_write;
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if ((WRENW == 1) || wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
ram[waddr] <= ram_n;
end
prev_write <= (| wren);
prev_data <= ram[waddr];

4
hw/rtl/mem/VX_mem_bus_if.sv
View file

@ -2,9 +2,9 @@
interface VX_mem_bus_if #(
parameter DATA_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8,
parameter ADDR_WIDTH = `MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8
parameter TAG_WIDTH = 1
) ();
wire req_valid;

2
hw/syn/altera/quartus/cache/Makefile vendored
View file

@ -4,4 +4,4 @@ SRC_FILE = VX_cache_cluster.sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache