github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-24 13:57:17 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix e2e building issues and increase division pipeline length

Browse source
This commit is contained in:
wgulian3 2020-02-19 01:04:48 -05:00
parent e76d05f7ce
commit 3423e3189f
4 changed files with 12 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
rtl/VX_alu.v
View file

@ -14,9 +14,9 @@ module VX_alu(
output reg out_alu_stall
);
localparam div_pipeline_len = 3;
localparam div_pipeline_len = 10;
wire[31:0] unsigned_div_result;
wire[31:0] unsigned_div_result;
wire[31:0] unsigned_rem_result;
wire[31:0] signed_div_result;
wire[31:0] signed_rem_result;

4
rtl/quartus/Makefile
View file

@ -33,6 +33,7 @@ STAMP = echo done >
$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl
$(STAMP) fit.chg
$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
@ -45,6 +46,7 @@ $(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
smart.log: $(PROJECT_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
@ -69,4 +71,4 @@ program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox bin/

4
rtl/quartus/make_pins_virtual.tcl
View file

@ -2,10 +2,12 @@ load_package flow
package require cmdline
project_open Vortex
proc make_all_pins_virtual { args } {
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
# execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {

4
rtl/quartus/project.tcl
View file

@ -107,6 +107,10 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set where [file dirname [info script]]
source [file join $where make_pins_virtual.tcl]
project_close
# set_global_assignment -name VERILOG_FILE $opts(src)