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Fix issues quartus synthesis issues

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This commit is contained in:
wgulian3 2020-02-18 13:24:18 -05:00
parent d71f8fcc73
commit e76d05f7ce
6 changed files with 15 additions and 10 deletions
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10
rtl/VX_alu.v
View file

@ -28,8 +28,8 @@ module VX_alu(
.PIPELINE(div_pipeline_len)
) unsigned_div (
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(unsigned_div_result),
@ -45,8 +45,8 @@ module VX_alu(
.PIPELINE(div_pipeline_len)
) signed_div (
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(signed_div_result),
@ -209,4 +209,4 @@ module VX_alu(
end
`endif
endmodule : VX_alu
endmodule : VX_alu

4
rtl/VX_csr_data.v
View file

@ -57,7 +57,7 @@ module VX_csr_data (
always @(posedge clk or posedge reset) begin
if (reset) begin
for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
assign csr[curr_e] = 0;
csr[curr_e] <= 0;
end
cycle <= 0;
instret <= 0;
@ -79,4 +79,4 @@ module VX_csr_data (
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[in_read_csr_address]};
endmodule
endmodule

3
rtl/VX_csr_pipe.v
View file

@ -1,3 +1,4 @@
`include "VX_define.v"
module VX_csr_pipe (
input wire clk, // Clock
@ -102,4 +103,4 @@ module VX_csr_pipe (
assign VX_csr_wb.wb = wb_s2;
assign VX_csr_wb.csr_result = final_csr_data;
endmodule
endmodule

4
rtl/compat/VX_divide.v
View file

@ -49,7 +49,7 @@ module VX_divide
.numer(numer),
.denom(denom),
.quotient(quotient),
.remainder(remainder)
.remain(remainder)
);
end
@ -135,4 +135,4 @@ module VX_divide
end
endgenerate
endmodule : VX_divide
endmodule : VX_divide

1
rtl/quartus/project.tcl
View file

@ -70,6 +70,7 @@ set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v

3
rtl/quartus/vortex.sdc
View file

@ -4,3 +4,6 @@ create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty