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felsabbagh3 2020-03-03 02:49:30 -08:00
parent 3a970bbe7b
commit 361fc2c3fe
5 changed files with 457 additions and 17 deletions
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172
rtl/VX_cache/VX_bank.v
View file

@ -5,6 +5,7 @@ module VX_bank (
input wire reset,
// Input Core Request
input wire delay_req,
input wire [`NUMBER_REQUESTS-1:0] bank_valids,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
@ -13,6 +14,7 @@ module VX_bank (
input wire [`NW_M1:0] bank_warp_num,
input wire [2:0] bank_mem_read,
input wire [2:0] bank_mem_write,
output wire reqq_full,
// Output Core WB
input wire bank_wb_pop,
@ -31,6 +33,7 @@ module VX_bank (
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram WB Requests
input wire dram_wb_queue_pop,
@ -39,4 +42,171 @@ module VX_bank (
output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
);
endmodule
wire dfpq_pop; // Use this
wire dfpq_empty;
wire dfpq_full;
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0;
assign dram_fill_accept = !dfpq_full;
VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
.in_data ({dram_fill_addr, dram_fill_rsp_data}),
.pop (dfpq_pop),
.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
.empty (dfpq_empty),
.full (dfpq_full)
);
wire reqq_pop; // Use this
wire reqq_push;
wire reqq_empty;
wire reqq_req_st0;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0;
wire [31:0] reqq_req_addr_st0;
wire [31:0] reqq_req_writeword_st0;
wire [4:0] reqq_req_rd_st0;
wire [1:0] reqq_req_wb_st0;
wire [`NW_M1:0] reqq_req_warp_num_st0;
wire [2:0] reqq_req_mem_read_st0;
wire [2:0] reqq_req_mem_write_st0;
assign reqq_push = !delay_req && (|bank_valids);
VX_cache_req_queue mrvq_queue(
.clk (clk),
.reset (reset),
// Enqueue
.reqq_push (reqq_push),
.bank_valids (bank_valids),
.bank_addr (bank_addr),
.bank_writedata (bank_writedata),
.bank_rd (bank_rd),
.bank_wb (bank_wb),
.bank_warp_num (bank_warp_num),
.bank_mem_read (bank_mem_read),
.bank_mem_write (bank_mem_write),
// Dequeue
.reqq_pop (reqq_pop),
.reqq_req_st0 (reqq_req_st0),
.reqq_req_tid_st0 (reqq_req_tid_st0),
.reqq_req_addr_st0 (reqq_req_addr_st0),
.reqq_req_writedata_st0(reqq_req_writeword_st0),
.reqq_req_rd_st0 (reqq_req_rd_st0),
.reqq_req_wb_st0 (reqq_req_wb_st0),
.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_empty (reqq_empty),
.reqq_full (reqq_full)
);
wire mrvq_pop; // Use this
wire mrvq_full;
wire mrvq_valid_st0;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
wire [31:0] mrvq_addr_st0;
wire [31:0] mrvq_writeword_st0;
wire [4:0] mrvq_rd_st0;
wire [1:0] mrvq_wb_st0;
wire [`NW_M1:0] mrvq_warp_num_st0;
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
VX_cache_miss_resrv mrvq_queue(
.clk (clk),
.reset (reset),
// Enqueue
.miss_add (miss_add), // Need to do all
.miss_add_addr (miss_add_addr),
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_rd (miss_add_rd),
.miss_add_wb (miss_add_wb),
.miss_add_warp_num (miss_add_warp_num),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_resrv_full (mrvq_full)
// Broadcast
.is_fill_st1 (is_fill_st1),
.fill_addr_st1 (addr_st1),
// Dequeue
.miss_resrv_pop (mrvq_pop),
.miss_resrv_valid_st0 (mrvq_valid_st0),
.miss_resrv_addr_st0 (mrvq_addr_st0),
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_rd_st0 (mrvq_rd_st0),
.miss_resrv_wb_st0 (mrvq_wb_st0),
.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
wire stall_st0;
wire stall_st1;
wire stall_st2;
assign stall_st1 = stall_st2;
assign stall_st0 = stall_st1;
assign dfpq_pop = !dfpq_empty && !stall_st0;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0;
assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0;
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [31:0] qual_addr_st0;
wire [31:0] qual_writeword_st0;
wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0;
wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
wire is_fill_st1;
wire valid_st1;
wire [31:0] addr_st1;
wire [31:0] writeword_st1;
wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1;
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1;
assign qual_is_fill_st0 = dfpq_pop;
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop;
assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
mrvq_pop ? mrvq_addr_st0 :
reqq_pop ? reqq_req_addr_st0 :
0;
assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
reqq_pop ? reqq_req_writeword_st0 :
0;
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} :
0;
VX_generic_register #(.N(1)) s0_1 (
.clk (clk),
.reset(reset),
.stall(stall_st1),
.flush(0),
.in ({qual_is_fill_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_writedata_st0, qual_inst_meta_st0}),
.out ({is_fill_st1 , valid_st1 , addr_st1 , writeword_st1 , writedata_st1 , inst_meta_st1 })
);
endmodule

40
rtl/VX_cache/VX_cache.v
View file

@ -16,6 +16,7 @@ module VX_cache (
input wire [4:0] core_req_rd,
input wire [1:0] core_req_wb,
input wire [`NW_M1:0] core_req_warp_num,
output wire delay_req,
// Core Writeback
input wire core_no_wb_slot,
@ -30,6 +31,7 @@ module VX_cache (
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram request
output wire dram_req,
@ -53,12 +55,20 @@ module VX_cache (
wire dfqq_full;
wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_accept;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
wire[`NUMBER_BANKS-1:0] per_bank_reqq_full;
assign delay_req = (|per_bank_reqq_full);
assign dram_fill_accept = (`NUMBER_BANKS == 1) ? dram_fill_accept[0] : dram_fill_accept[dram_fill_addr[`BANK_SELECT_ADDR_RNG]];
VX_cache_dram_req_arb VX_cache_dram_req_arb(
.clk (clk),
.reset (reset),
@ -122,6 +132,7 @@ module VX_cache (
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_accept;
wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req;
@ -132,15 +143,18 @@ module VX_cache (
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
wire curr_bank_reqq_full;
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
assign curr_bank_writedata = core_req_writedata;
assign curr_bank_rd = core_req_rd;
assign curr_bank_wb = core_req_wb;
assign curr_bank_warp_num = core_req_warp_num;
assign curr_bank_mem_read = core_req_mem_read;
assign curr_bank_mem_write = core_req_mem_write;
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
assign curr_bank_writedata = core_req_writedata;
assign curr_bank_rd = core_req_rd;
assign curr_bank_wb = core_req_wb;
assign curr_bank_warp_num = core_req_warp_num;
assign curr_bank_mem_read = core_req_mem_read;
assign curr_bank_mem_write = core_req_mem_write;
assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
// Core WB
assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
@ -156,9 +170,10 @@ module VX_cache (
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept;
// Dram writeback request
assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
@ -171,6 +186,7 @@ module VX_cache (
.clk (clk),
.reset (reset),
// Core req
.delay_req (delay_req),
.bank_valids (curr_bank_valids),
.bank_addr (curr_bank_addr),
.bank_writedata (curr_bank_writedata),
@ -179,6 +195,7 @@ module VX_cache (
.bank_warp_num (curr_bank_warp_num),
.bank_mem_read (curr_bank_mem_read),
.bank_mem_write (curr_bank_mem_write),
.reqq_full (curr_bank_reqq_full),
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
@ -197,6 +214,7 @@ module VX_cache (
.dram_fill_rsp (curr_bank_dram_fill_rsp),
.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
.dram_fill_accept (curr_bank_dram_fill_accept),
// Dram writeback
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),

14
rtl/VX_cache/VX_cache_config.v
View file

@ -10,16 +10,16 @@
`define CACHE_SIZE_BYTES 1024
// Size of line inside a bank in bytes
`define BANK_LINE_SIZE_BYTES 16
// Number of banks
// Number of banks {1, 2, 4, 8,...}
`define NUMBER_BANKS 8
// Size of a word in bytes
`define WORD_SIZE_BYTES 4
// Number of Word requests per cycle
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define NUMBER_REQUESTS `NT
// Number of cycles to complete stage 2 (read from memory)
`define STAGE_2_CYCLES 1
// Queues feeding into banks Knobs
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`define REQQ_SIZE `NT*`NW
@ -28,11 +28,11 @@
// Dram Fill Rsp Queue Size
`define DFPQ_SIZE 2
// Queues for writebacks Knobs
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`define CWBQ_SIZE `REQQ_SIZE
// Dram Writeback Queue Size
`define DWBQ_SIZE 2
`define DWBQ_SIZE 4
// Dram Fill Req Queue Size
`define DFQQ_SIZE `REQQ_SIZE
@ -41,6 +41,10 @@
// ========================================= Configurable Knobs =========================================
// data tid rd wb warp_num read write
`define MRVQ_METADATA_SIZE (32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(`NUMBER_REQUESTS))
`define vx_clog2_h(value, x) (value == (1 << x)) ? (x)

109
rtl/VX_cache/VX_cache_miss_resrv.v Normal file
View file

@ -0,0 +1,109 @@
`include "VX_cache_config.v"
module VX_cache_miss_resrv (
input wire clk,
input wire reset,
// Miss enqueue
input wire miss_add,
input wire[31:0] miss_add_addr,
input wire[31:0] miss_add_data,
input wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid,
input wire[4:0] miss_add_rd,
input wire[1:0] miss_add_wb,
input wire[`NW_M1:0] miss_add_warp_num,
input wire[2:0] miss_add_mem_read,
input wire[2:0] miss_add_mem_write,
output wire miss_resrv_full,
// Broadcast Fill
input wire is_fill_st1,
input wire[31:0] fill_addr_st1,
// Miss dequeue
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[31:0] miss_resrv_addr_st0,
output wire[31:0] miss_resrv_data_st0,
output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[4:0] miss_resrv_rd_st0,
output wire[1:0] miss_resrv_wb_st0,
output wire[`NW_M1:0] miss_resrv_warp_num_st0,
output wire[2:0] miss_resrv_mem_read_st0,
output wire[2:0] miss_resrv_mem_write_st0
);
// Size of metadata = 32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1)
reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0];
reg[`MRVQ_SIZE-1:0][31:0] addr_table;
reg[`MRVQ_SIZE-1:0] valid_table;
reg[`MRVQ_SIZE-1:0] ready_table;
assign miss_resrv_full = !(&valid_table);
wire enqueue_possible;
wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index;
VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) enqueue_picker(
.valids(~valid_table),
.index (enqueue_index),
.found (enqueue_possible)
);
reg[`MRVQ_SIZE-1:0] make_ready;
genvar curr_e;
generate
for (curr_e = 0; curr_e < `MRVQ_SIZE; curr_e=curr_e+1) begin
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e]
&& addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START];
end
endgenerate
wire dequeue_possible;
wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index;
wire[`MRVQ_SIZE-1:0] dequeue_valid = valid_table & ready_table;
VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) dequeue_picker(
.valids(dequeue_valid),
.index (dequeue_index),
.found (dequeue_possible)
);
assign miss_resrv_valid_st0 = dequeue_possible;
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
wire update_ready = (|make_ready);
integer i;
always @(posedge clk or reset) begin
if (reset) begin
for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0;
valid_table <= 0;
ready_table <= 0;
addr_table <= 0;
end else begin
if (miss_add && enqueue_possible) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write};
end
if (update_ready) begin
ready_table = ready_table | make_ready;
end
if (miss_resrv_pop && dequeue_possible) begin
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;
metadata_table[dequeue_index] <= 0;
end
end
end
endmodule

139
rtl/VX_cache/VX_cache_req_queue.v Normal file
View file

@ -0,0 +1,139 @@
`include "VX_cache_config.v"
module VX_cache_req_queue (
input wire clk,
input wire reset,
// Enqueue Data
input wire reqq_push,
input wire [`NUMBER_REQUESTS-1:0] bank_valids,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
input wire [4:0] bank_rd,
input wire [1:0] bank_wb,
input wire [`NW_M1:0] bank_warp_num,
input wire [2:0] bank_mem_read,
input wire [2:0] bank_mem_write,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [31:0] reqq_req_writedata_st0,
output wire [4:0] reqq_req_rd_st0,
output wire [1:0] reqq_req_wb_st0,
output wire [`NW_M1:0] reqq_req_warp_num_st0,
output wire [2:0] reqq_req_mem_read_st0,
output wire [2:0] reqq_req_mem_write_st0,
// State Data
output wire reqq_empty,
output wire reqq_full
);
wire [`NUMBER_REQUESTS-1:0] out_per_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] out_per_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] out_per_writedata;
wire [4:0] out_per_rd;
wire [1:0] out_per_wb;
wire [`NW_M1:0] out_per_warp_num;
wire [2:0] out_per_mem_read;
wire [2:0] out_per_mem_write;
reg [`NUMBER_REQUESTS-1:0] use_per_valids;
reg [`NUMBER_REQUESTS-1:0][31:0] use_per_addr;
reg [`NUMBER_REQUESTS-1:0][31:0] use_per_writedata;
reg [4:0] use_per_rd;
reg [1:0] use_per_wb;
reg [`NW_M1:0] use_per_warp_num;
reg [2:0] use_per_mem_read;
reg [2:0] use_per_mem_write;
wire [`NUMBER_REQUESTS-1:0] qual_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] qual_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] qual_writedata;
wire [4:0] qual_rd;
wire [1:0] qual_wb;
wire [`NW_M1:0] qual_warp_num;
wire [2:0] qual_mem_read;
wire [2:0] qual_mem_write;
wire[`NUMBER_REQUESTS-1:0] updated_valids;
wire use_empty = !(|use_per_valids);
wire out_empty = !(|out_per_valids);
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
VX_generic_queue #(.DATAW(`NUMBER_REQUESTS * (1+32+32+5+2+(`NW_M1+1)+3+3)), .SIZE(`REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({bank_valids, bank_addr, bank_writedata, bank_rd, bank_wb, bank_warp_num, bank_mem_read, bank_mem_write}),
.pop (pop_qual),
.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}),
.empty (reqq_empty),
.full (reqq_full)
);
assign qual_valids = use_empty ? out_per_valids : use_per_valids;
assign qual_addr = use_empty ? out_per_addr : use_per_addr;
assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata;
assign qual_rd = use_empty ? out_per_rd : use_per_rd;
assign qual_wb = use_empty ? out_per_wb : use_per_wb;
assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num;
assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read;
assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(.N(`NUMBER_REQUESTS)) VX_sel_bank(
.valids(qual_valids),
.index (qual_request_index),
.found (qual_has_request)
);
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_addr_st0 = qual_addr [qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
assign reqq_req_rd_st0 = qual_rd;
assign reqq_req_wb_st0 = qual_wb;
assign reqq_req_warp_num_st0 = qual_warp_num
assign reqq_req_mem_read_st0 = qual_mem_read;
assign reqq_req_mem_write_st0 = qual_mem_write;
assign updated_valids = qual_valids & (~(1 << qual_request_index));
always @(posedge clk or reset) begin
if (reset) begin
use_per_valids <= 0;
use_per_addr <= 0;
use_per_writedata <= 0;
use_per_rd <= 0;
use_per_wb <= 0;
use_per_warp_num <= 0;
use_per_mem_read <= 0;
use_per_mem_write <= 0;
end else begin
if (reqq_pop && qual_has_request) begin
use_per_valids <= updated_valids;
use_per_addr <= qual_addr;
use_per_writedata <= qual_writedata;
use_per_rd <= qual_rd;
use_per_wb <= qual_wb;
use_per_warp_num <= qual_warp_num;
use_per_mem_read <= qual_mem_read;
use_per_mem_write <= qual_mem_write;
end
end
end
endmodule