github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-24 05:47:35 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis

Browse source
This commit is contained in:
wgulian3 2020-02-19 01:04:55 -05:00
commit 3b60c10460
1 changed files with 8 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

11
rtl/VX_csr_data.v
View file

@ -57,7 +57,12 @@ module VX_csr_data (
always @(posedge clk or posedge reset) begin
if (reset) begin
for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
`ifdef VERILATOR
// - Verilator does not support delayed assignment in loops.
csr[curr_e] = 0;
`else
csr[curr_e] <= 0;
`endif
end
cycle <= 0;
instret <= 0;
@ -74,9 +79,9 @@ module VX_csr_data (
assign out_read_csr_data = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[in_read_csr_address]};
endmodule
endmodule : VX_csr_data