Cleared a few RTL warnings

hw/rtl/VX_cluster.sv

@@ -66,7 +66,7 @@ module VX_cluster #(
 
     // simulation helper signals
     output wire                 sim_ebreak,
-    output wire [`NUM_REGS-1:0][31:0] sim_wb_value,
+    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
 
     // Status
     output wire                 busy
@@ -449,7 +449,7 @@ module VX_cluster #(
     ///////////////////////////////////////////////////////////////////////////
 
     wire [`NUM_SOCKETS-1:0] per_socket_sim_ebreak;
-    wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][31:0] per_socket_sim_wb_value;
+    wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_socket_sim_wb_value;
     assign sim_ebreak = per_socket_sim_ebreak[0];
     assign sim_wb_value = per_socket_sim_wb_value[0];
     `UNUSED_VAR (per_socket_sim_ebreak)

hw/rtl/VX_gpu_types.vh

@@ -69,7 +69,7 @@ localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(ICACHE_NUM_REQ
 ////////////////////////// Dcache Parameters //////////////////////////////////
 
 // Word size in bytes
-localparam DCACHE_WORD_SIZE	    = 8;
+localparam DCACHE_WORD_SIZE	    = 4;
 localparam DCACHE_ADDR_WIDTH	= (`XLEN - `CLOG2(DCACHE_WORD_SIZE));
 
 // Block size in bytes

hw/rtl/VX_socket.sv

@@ -58,7 +58,7 @@ module VX_socket #(
 
     // simulation helper signals
     output wire             sim_ebreak,
-    output wire [`NUM_REGS-1:0][31:0] sim_wb_value,
+    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
 
     // Status
     output wire             busy
@@ -307,7 +307,7 @@ module VX_socket #(
     ///////////////////////////////////////////////////////////////////////////
 
     wire [`SOCKET_SIZE-1:0] per_core_sim_ebreak;
-    wire [`SOCKET_SIZE-1:0][`NUM_REGS-1:0][31:0] per_core_sim_wb_value;
+    wire [`SOCKET_SIZE-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_core_sim_wb_value;
     assign sim_ebreak = per_core_sim_ebreak[0];
     assign sim_wb_value = per_core_sim_wb_value[0];
     `UNUSED_VAR (per_core_sim_ebreak)

hw/rtl/Vortex.sv

@@ -116,9 +116,9 @@ module Vortex (
 `endif
 
     wire sim_ebreak /* verilator public */;
-    wire [`NUM_REGS-1:0][31:0] sim_wb_value /* verilator public */;    
+    wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */;    
     wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
-    wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][31:0] per_cluster_sim_wb_value;
+    wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value;
     assign sim_ebreak = per_cluster_sim_ebreak[0];
     assign sim_wb_value = per_cluster_sim_wb_value[0];
     `UNUSED_VAR (per_cluster_sim_ebreak)

hw/rtl/core/VX_alu_unit.sv

@@ -129,7 +129,7 @@ module VX_alu_unit #(
     wire is_jal = is_br_op && (br_op == `INST_BR_JAL || br_op == `INST_BR_JALR);
     wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : trunc_alu_result; 
 
-    wire [31:0] br_dest    = add_result[alu_req_if.tid][31:0];
+    wire [`XLEN-1:0] br_dest    = add_result[alu_req_if.tid][`XLEN-1:0];
     wire [32:0] cmp_result = sub_result[alu_req_if.tid][32:0];
     
     wire is_less  = cmp_result[32];
@@ -163,7 +163,7 @@ module VX_alu_unit #(
     assign alu_ready_in = alu_ready_out || ~alu_valid_out;
 
     VX_pipe_register #(
-        .DATAW  (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + 32),
+        .DATAW  (1 + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + `XLEN),
         .RESETW (1)
     ) pipe_reg (
         .clk      (clk),

hw/rtl/core/VX_core.sv

@@ -445,7 +445,7 @@ module VX_core_top #(
 
     // simulation helper signals
     output wire                             sim_ebreak,
-    output wire [`NUM_REGS-1:0][31:0]       sim_wb_value,
+    output wire [`NUM_REGS-1:0][`XLEN-1:0]       sim_wb_value,
 
     // Status
     output wire                             busy

hw/rtl/core/VX_csr_unit.sv

@@ -1,5 +1,6 @@
 `include "VX_define.vh"
 `include "VX_gpu_types.vh"
+`include "VX_config.vh"
 
 `IGNORE_WARNINGS_BEGIN
 import VX_gpu_types::*;
@@ -58,12 +59,12 @@ module VX_csr_unit #(
     localparam NW_WIDTH   = `UP(`NW_BITS);
 
     
-    reg [`NUM_THREADS-1:0][31:0]      csr_read_data;
-    reg [31:0]                        csr_write_data;
-    wire [31:0]                       csr_read_data_ro, csr_read_data_rw;
-    wire [31:0]                       csr_req_data;
-    reg                               csr_rd_enable;
-    wire                              csr_wr_enable;    
+    reg [`NUM_THREADS-1:0][`XLEN-1:0]      csr_read_data;
+    reg  [`XLEN-1:0]                       csr_write_data;
+    wire [`XLEN-1:0]                       csr_read_data_ro, csr_read_data_rw;
+    wire [`XLEN-1:0]                       csr_req_data;
+    reg                                    csr_rd_enable;
+    wire                                   csr_wr_enable;    
 
     `UNUSED_VAR (gpu_pending)
     wire csr_access_pending = (0    
@@ -217,7 +218,7 @@ module VX_csr_unit #(
 
     // CSR write
 
-    assign csr_req_data = csr_req_if.use_imm ? 32'(csr_req_if.imm) : csr_req_if.rs1_data[csr_req_if.tid];
+    assign csr_req_data = csr_req_if.use_imm ? `XLEN'(csr_req_if.imm) : csr_req_if.rs1_data[csr_req_if.tid];
 
     assign csr_wr_enable = (csr_write_enable || (csr_req_data != 0))
                 `ifdef EXT_ROP_ENABLE

hw/rtl/core/VX_dispatch.sv

@@ -67,12 +67,12 @@ module VX_dispatch (
     wire lsu_is_fence = `INST_LSU_IS_FENCE(dispatch_if.op_mod);
 
     // USED TO TRUNCATE IMMEDIATE and RS1 TO 32 BITS
-    wire [31:0] trunc_ibuffer_imm = ibuffer_if.imm[31:0];
-    wire [`NUM_THREADS-1:0][31:0] trunc_rs1;
+    wire [`XLEN-1:0] trunc_ibuffer_imm = ibuffer_if.imm[`XLEN-1:0];
+    wire [`NUM_THREADS-1:0][`XLEN-1:0] trunc_rs1;
 
     for (genvar i = 0; i < `NUM_THREADS; ++i) begin
         // These values are used for PC calculations, so should stay as 32 bits
-        assign trunc_rs1[i] = gpr_rsp_if.rs1_data[i][31:0];
+        assign trunc_rs1[i] = gpr_rsp_if.rs1_data[i][`XLEN-1:0];
     end
 
     VX_skid_buffer #(
@@ -97,8 +97,8 @@ module VX_dispatch (
     wire [`NRI_BITS-1:0] csr_imm = dispatch_if.imm[`CSR_ADDR_BITS +: `NRI_BITS];
 
     // USED TO TRUNCATE CSRs TO 32 BITS. I DONT KNOW IF THIS IS CORRECT???
-
-    wire [31:0] csr_rs1_data = gpr_rsp_if.rs1_data[tid][31:0]; // CSR stays 32 bits
+    // Commenting this to fix a warning because this csr_rs1_data signal is not being used anywhere else. -Jaswanth
+    // wire [31:0] csr_rs1_data = gpr_rsp_if.rs1_data[tid][31:0]; // CSR stays 32 bits
 
     VX_skid_buffer #(
         .DATAW   (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `INST_CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NRI_BITS + `UP(`NT_BITS) + (`NUM_THREADS * `XLEN)),

hw/rtl/core/VX_icache_stage.sv

@@ -82,7 +82,7 @@ module VX_icache_stage #(
     // Icache Request
     
     assign icache_req_valid = ifetch_req_if.valid && ~pending_ibuf_full[ifetch_req_if.wid];
-    assign icache_req_addr  = ifetch_req_if.PC[31:2];
+    assign icache_req_addr  = ICACHE_ADDR_WIDTH'(ifetch_req_if.PC[31:2]);
     assign icache_req_tag   = {ifetch_req_if.uuid, req_tag};
     assign ifetch_req_if.ready = icache_req_ready && ~pending_ibuf_full[ifetch_req_if.wid];
 

hw/rtl/core/VX_warp_sched.sv

@@ -98,7 +98,7 @@ module VX_warp_sched #(
             // join handling
             if (join_if.valid) begin
                 if (join_else) begin
-                    warp_pcs[join_if.wid] <= join_pc;
+                    warp_pcs[join_if.wid] <= `XLEN'(join_pc);
                 end
                 thread_masks[join_if.wid] <= join_tmask;
             end
@@ -151,7 +151,7 @@ module VX_warp_sched #(
             end
 
             if (ifetch_req_fire) begin
-                warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
+                warp_pcs[ifetch_req_if.wid] <= `XLEN'(ifetch_req_if.PC + 32'(4));
             end
 
             if (wrelease_if.valid) begin
@@ -241,13 +241,13 @@ module VX_warp_sched #(
         .valid_out (schedule_valid)
     );
 
-    wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data;
+    wire [`NUM_WARPS-1:0][(`NUM_THREADS + `XLEN)-1:0] schedule_data;
     for (genvar i = 0; i < `NUM_WARPS; ++i) begin
         assign schedule_data[i] = {(use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]),
-                                   (use_wspawn[i] ? wspawn_pc : warp_pcs[i])};
+                                   (use_wspawn[i] ? `XLEN'(wspawn_pc) : warp_pcs[i])};
     end
 
-    assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid];    
+    assign {schedule_tmask, schedule_pc} = {schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-1:(`NUM_THREADS + `XLEN)-4], schedule_data[schedule_wid][(`NUM_THREADS + 32)-5:0]};
 
 `ifndef NDEBUG
     assign instr_uuid = UUID_WIDTH'(issued_instrs[schedule_wid] * `NUM_WARPS * `NUM_CORES * `NUM_CLUSTERS)

third_party/cocogfx

@@ -1 +1 @@
-Subproject commit e4656d62878e517e743e891d22628c9191dca6bc
+Subproject commit 6448e68330ca00a64ab3184e3c5c95b59fe8b62a